• Journal of Sensor Science and Technology
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• 제27권6호
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• Journal of the Korean Institute of Navigation
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• 제19권3호
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• pp.21-28
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• 1995

Mathematical morphology skeleton image processing makes many partial skeleton image planes from an original binary image. And the original binary image can be reconstructed without any distortion by summing the first partial skeleton image plane and each dilated partial skeleton image planes using the same structuring element. Especially compression effects of Elias coding to the morphological globally minimal skeleton(GMS) image, is better than that of PCX and Huffman coding. And then this paper proposes mathematical morphological GMS image processing which can be applied to a binary image transmitting for facimile and big size(bigger than $64{\times}64$ size) bitmap fonts storing in a memory.

• Journal of Animal Environmental Science
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• 제5권2호
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• pp.93-100
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• 1999

Pig's original image data was transformed to a binary image, an image excluding head and tail portion from the whole binary image, and a projected image associated with pig's height. Then the length of body, width of shoulder, and area of pig were calculated and the relationships among the above characteristics and pig's weight were analyzed. The results obtained from this study were as follows: 1. Whole binary image data was considered to be improper to determine the pig's weight because the movement of pig's head and tail portion affected the image data. 2. Binary image data excluding head and tail portion from the whole binary image showed a better estimation of the pig's weight than the whole binary image. 3. Pig's should width was analyzed to be improper factor to determine the pig's weight. 4. The projected image associated with pig's height showed the highest correlation between the pig's area of the image and pig's weight(R2=0.9965). From this research the projected image associated with pig's height, which is excluding head and tail portion from the whole body of pig's image, was considered to be the prime factor to measure the pig's weight by the noncontact measurement.

• Journal of Korea Multimedia Society
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• 제19권6호
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• pp.1043-1051
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• 2016

In this paper, double encryption technique of binary image using random phase mask and 2-step phase-shifting digital holography is proposed. After phase modulating of binary image, firstly, random phase mask to be used as key image is generated through the XOR operation with the binary phase image. And the first encrypted image is encrypted again through the fresnel transform and 2-step phase-shifting digital holography. In the decryption, simple arithmetic operation and inverse Fresnel transform are used to get the first decryption image, and second decryption image is generated through XOR operation between first decryption image and key image. Finally, the original binary image is recovered through phase modulation.

• Journal of Sensor Science and Technology
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• 제30권5호
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• pp.295-299
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• 2021

In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제9권3호
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• pp.37-43
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• 2009

In this paper, we proposed that a novel method base on a binary image that technique is proposed for data hiding into binary images and halftone image. A binary image is bitmap image and halftone is composed by two-tone value in a limited region in an image. For this reason, it is not easy to hide messages in binary images. PWLC is a new method to hide a message in binary images. However, it yields images of unacceptable quality, unless you should change very few of it. Therefore, in order to solve this problem, we used run-length method into binary images. That is, we find a proper region to hide messages. In this paper, we proposed new method to hide messages in binary images. In addition, we proved that our algorithm is better than PWLC through the experiment.

• Journal of the Korean Society for Precision Engineering
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• 제20권7호
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• pp.120-127
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• 2003

A novel three degrees of freedom sensing method utilizing binary grid pattern image and vision camera is presented. The binary grid pattern image is designed by Pseudo-Random Binary Arrays and referenced to encode in-plane position of a moving stage of the contact-free planar actuator. First, the yaw motion of the stage is detected using fast image processing and then the other planar positions, x and y, are decoded with a sequence of images. This method can be applied to the system that needs feedback of in-plane position, with advantages of a good accuracy and high resolution comparable with the encoder, a relatively compact structure, no friction, and a low cost. In this paper, all the procedures of the above sensing mechanism are described in detail, including simulation and experiment results.

• Journal of KIISE
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• 제44권12호
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• pp.1313-1318
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• 2017

Aggregating local features in a single vector is a fundamental problem in an image search. In this process, the image search process can be speeded up if binary features which are extracted almost two order of magnitude faster than gradient-based features are utilized. However, in order to utilize the binary features in an image search, it is necessary to study the techniques for clustering binary features to generate binary visual words. This investigation is necessary because traditional clustering techniques for gradient-based features are not compatible with binary features. To this end, this paper studies the techniques for clustering binary features for the purpose of generating binary visual words. Through experiments, we analyze the trade-off between the accuracy and computational efficiency of an image search using binary features, and we then compare the proposed techniques. This research is expected to be applied to mobile applications, real-time applications, and web scale applications that require a fast image search.

• Journal of Multimedia Information System
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• 제5권2호
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• pp.131-138
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• 2018

This work describes a binary image based fast Difference of Gaussian (DoG) filter using zero-dimensional (0-d) convolution and state machine look up tables (LUTs) for image and video stitching hardware platforms. The proposed approach for using binary images to obtain DoG filtering can significantly reduce the data size compared to conventional gray scale based DoG filters, yet binary images still preserve the key features of the image such as contours, edges, and corners. Furthermore, the binary image based DoG filtering can be realized with zero-dimensional convolution and state machine LUTs which eliminates the major portion of the adder and multiplier blocks that are generally used in conventional DoG filter hardware engines. This enables fast computation time along with the data size reduction which can lead to compact and low power image and video stitching hardware blocks. The proposed DoG filter using binary images has been implemented with a FPGA (Altera DE2-115), and the results have been verified.

• Journal of Sensor Science and Technology
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• 제30권1호
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• pp.61-65
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• 2021

In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.