• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.6
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• pp.259-265
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• 2014

When the trace-driven simulation is used for the performance analysis of widely used multicore processors in the initial design stage, much time and disk space is necessary. In this paper, statistical simulations are performed for a high performance multicore processor with various hardware configurations. For the experiment, SPEC2000 benchmarks programs are used for profiling and synthesizing new instruction traces. As a result, the performance obtained by our statistical simulation is comparable to that of the trace-driven simulation with the benefit of tremendous reduction in the simulation time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.219-224
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• 2015

Recently, the multi-core processor architecture is widely used in the digital signal processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multi-core processors are known to have higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core digital signal processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric quad-core, octa-core and hexadeca-core digital signal processors and compared with the symmetric ones of similar hardware budget using UTDSP benchmarks as input.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1215-1228
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• 1996

The purpose of benchmark program is to measure the performance of a computer system. The performance of a computer system is determined by the amount of execution time of user application programs. Thus, it is assumed that a benchmark program must have the same features with user application programs to test. In this paper, we have designed and implemented CMFstone which is consisted of Chaustone, Mchaustone and Fhsstone. After applied the CMFstone, designed and implemented in this paper, to the real situations, the results of comparison show that CMFstone is similar to geometric mean of other benchmarks results. Thus, we have concluded that CMFstone is good enough to measure the performance of a computer system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.53-64
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• 2004

As to medium data which is involved in the form of streaming for a multimedia application, it characterizes that spatial locality occurs strongly but temporal locality appears even weaker. In this paper, with regard to dynamic prefetching, we suggest a method to make the most of memory reference regularities which typically innate by nature in the multimedia data with strong spatial locality but with weak temporal locality. Especially, the suggested method has a remarkable capability such that it can reduce prefetching errors substantially compared to existing prefetching methods for an application Program which divides an way into small sub-blocks and, plus executes in the unit of sub-block. We carried out experiments to test the suggested method using various MediaBench benchmarks. From the results, we have confirmed that the occurrences of prefetching error decrease effectively than those of existing linear prefetching methods.

• Journal of The Korean Association For Science Education
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• v.23 no.4
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• pp.401-418
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• 2003

The purpose of this study was to examine philosophical views on science of two influential curriculum documents, AAAS' s Benchmarks for Scientific Literacy (Benchmark) and NRC's National Science Education Standards (Standard), and to get educational implications about a desired philosophical view on science at a school science level. In order to determine the philosophical views on science explicitly suggested in the documents, Soh's Philosophical Perspectives Probe (PPP) was used as a framework for analysis. Forty preservice teachers reviewed the documents, extracting paragraphs with which statements of the PPP' s questions would agree. The results of the study were as follows: First, the Benchmark's philosophical view on science corresponds to the borderline between inductivism and eclecticism, or eclecticism close to falsificationism. The philosophical positions by the PPP' s themes are very different. Second, the Standard's philosophical position on science corresponds to inductivism close to eclecticism. Its philosophical position by the themes of the PPP is very different like the Benchmark. These results indicate that philosophical positions of the documents are more complex than popular conceptions would have it. That is to say, the results suggest that the science curriculum documents hold not only a contemporary philosophical view on science but also a traditional view on science, and that the philosophical positions on science are different from each other by documents and even by the PPP's themes in the same document. The results suggest that the philosophical views on science in school science contexts need to be adjusted and presented to K-12 students according to topics related to philosophy of science.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1169-1172
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm consider area and delay time is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. The proposed algorithm is examined by using benchmarks in SIS. In the case of that the number of OR-terms is 5, the experiments results show that reduce the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.3
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• pp.112-123
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• 2015

There are many systems for cutting plates or pipes into a desired shape. A typical system is a plasma cutter. It uses plasma, which means that an effective design of the table supporting the workpiece is an important issue in order to ensure a long operational career. Conventional roller-support worktables have a short lifespan due to scratches from the plasma, and it is also difficult to maintain the roller balance. By using a bolt-fastening method, deformation and failure of the final product can occur due to the stress concentration at bolting points. To escape these issues, a polygon support and bracket fastening method was designed. Due to polygons having a number of support surfaces, when one surface has been damaged, it is possible to reuse the support by utilizing a different surface. The bracket-fastening method can extend the worktable lifetime and increase productivity by reducing stress concentration. In this paper, the polygon support/bracket-fastening method is compared with existing technologies. Consequently, performance benchmarks are verified through a structure analysis and experimentation.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.2
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• pp.55-62
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• 2009

The power consumption of a high-end microprocessor increases very rapidly. High power consumption will lead to a rapid increase in the chip temperature as well. If the temperature reaches beyond a certain level, chip operation becomes either slow or unreliable. Therefore various approaches for Dynamic Thermal Management (DTM) have been proposed. In this paper, we propose a learning based temperature prediction scheme for a multi-core system. In this approach, from repeatedly executing an application, we learn the thermal patterns of the chip, and we control the temperature in advance through DTM. When the predicted temperature may go beyond a threshold value, we reduce the temperature by decreasing the operation frequencies of the corresponding core. We implement our temperature prediction on an Intel's Quad-Core system which has integrated digital thermal sensors. A Dynamic Frequency System (DFS) technique is implemented to have four frequency steps on a Linux kernel. We carried out experiments using Phoronix Test Suite benchmarks for Linux. The peak temperature has been reduced by on average $5^{\circ}C{\sim}7^{\circ}C$. The overall average temperature reduced from $72^{\circ}C$ to $65^{\circ}C$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.175-180
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• 2012

In order to overcome the complexity and performance limit problems of superscalar processors, the multicore architecture has been prevalent recently. The configuration and the size of instruction and data caches greatly gives effect on the performance of multicore processors. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the 2-core to 16-core architectures with different sizes of caches extensively. As a result, the 2-way set associative instruction and data cache with the size of 64KB brought the best cost-effective performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.163-169
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• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.