• Title/Summary/Keyword: Benchmarks

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Preprocessed Cholesky-Factor Downdatings for Observation Matrices (관측행렬에 대한 전처리 Cholesky-Factor Downdating 기법)

  • Kim, Suk-Il;Lee, Chung-Han;Jeon, Joong-Nam
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.2
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    • pp.359-368
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    • 1996
  • This paper introduces PGD(Preprocessed Givens Downdating)and PHD(Preprocessed Hyperbolic Downdating) algorithms, wherein a multiple-row observation matrix $Z^T$ is factorized into a partial Cholesky factor Rz, such that $Z^T$ = $Q_zR_z, Q_zQ^T_z=I$, and then Rz is recursively downdated by using GD(Givens Downdating)and HD(Hyperbolic Dondating), respectively. Time complexities of PGD and PHD algorithms are $pn^2$$5n^3/6$$pn^2$$n^3/3$ flops, respectively, if p$\geq$n, while those of the existing GD and HD are known to be $5pn^2/2$ and $2pn^2$ flops,, respectively. This concludes that the factorization of observation matrices, which we call preprocessing, would improve the overall performance of the downdating process. Benchmarks on the Sun SPARC/2 system also show that preprocessing would shorten the required downdating times compared to those of downdatings without preprocessing. Furthermore, benchmarks also show that PHD provides better performance than PGD.

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Improvement of Address Pointer Assignment in DSP Code Generation (DSP용 코드 생성에서 주소 포인터 할당 성능 향상 기법)

  • Lee, Hee-Jin;Lee, Jong-Yeol
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.45 no.1
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    • pp.37-47
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    • 2008
  • Exploitation of address generation units which are typically provided in DSPs plays an important role in DSP code generation since that perform fast address computation in parallel to the central data path. Offset assignment is optimization of memory layout for program variables by taking advantage of the capabilities of address generation units, consists of memory layout generation and address pointer assignment steps. In this paper, we propose an effective address pointer assignment method to minimize the number of address calculation instructions in DSP code generation. The proposed approach reduces the time complexity of a conventional address pointer assignment algorithm with fixed memory layouts by using minimum cost-nodes breaking. In order to contract memory size and processing time, we employ a powerful pruning technique. Moreover our proposed approach improves the initial solution iteratively by changing the memory layout for each iteration because the memory layout affects the result of the address pointer assignment algorithm. We applied the proposed approach to about 3,000 sequences of the OffsetStone benchmarks to demonstrate the effectiveness of the our approach. Experimental results with benchmarks show an average improvement of 25.9% in the address codes over previous works.

Three Strategies for Integrated Science Teaching of "Energy" Applying Knowledge, Social Problem, and Individual Interest Centered Approaches (지식내용, 사회문제, 개인흥미 중심의 통합과학교육 접근법을 적용한 '에너지' 주제의 교수.학습 전략 모색(I))

  • Lee, Mi-Hye;Son, Yeon-A;Pottenger III, Francis M.;Choi, Don-Hyung
    • Journal of The Korean Association For Science Education
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    • v.21 no.2
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    • pp.342-356
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    • 2001
  • Integrated science for high school is required in the present Korean National Sixth Curriculum and the Seventh Curriculum which will be effective in 2002. Currently, most science teachers in secondary school have concerns about teaching integrated science subjects and this continues to raise a significant problem for practical implementation of integrated science education in schools. In this paper, we discuss two reasons for these concerns that our analysis revealed: 1) Science teachers do not understand how to implement integrated science education and 2) there are insufficient teaching-learning materials supporting integrated science. Three different approaches to integration that have been suggested to overcome the problem of implementation are outlined here. They are the knowledge centered, social problem centered, and individual interest centered approaches. Reported here are the first two steps we undertook in preparation for testing the relative effectiveness of these approaches. First, we analyzed the content of the Korean Sixth and Seventh National Science Curricula, seven Korean integrated science text books, the American National Science Education Standards, and the American Association for the Advancement of Science Benchmarks looking for common themes. We identified in the analyzed materials the common themes: energy conservation, energy transformation, energy transport, energy degradation. We then used their energy related content to organize sets of concept structures, one set for each of the three approaches. These concept structures will provide the foundations for the development of integrated teaching-learning energy plans to be used in our research into the effectiveness of the approaches.

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Determination of the Optimal Height using the Simplex Algorithm in Network-RTK Surveying (Network-RTK측량에서 심플렉스해법을 이용한 최적표고 결정)

  • Lee, Suk Bae;Auh, Su Chang
    • Journal of Korean Society for Geospatial Information Science
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    • v.24 no.1
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    • pp.35-41
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    • 2016
  • GNSS/Geoid positioning technology allows orthometric height determination using both the geoidal height calculated from geoid model and the ellipsoidal height achieved by GNSS survey. In this study, Network-RTK surveying was performed through the Benchmarks in the study area to analyze the possibility of height positioning of the Network-RTK. And the orthometric heights were calculated by applying the Korean national geoid model KNGeoid13 according to the condition of with site calibration and without site calibration and the results were compared. Simplex algorithm was adopted for liner programming in this study and the heights of all Benchmarks were calculated in both case of applying site calibration and does not applying site calibration. The results were compared to Benchmark official height of the National Geographic Information Institute. The results showed that the average value of the height difference was 0.060m, and the standard deviation was 0.072m in Network-RTK without site calibration and the average value of the height difference was 0.040m, and the standard deviation was 0.047m in Network-RTK with the application of the site calibration. With linearization method to obtain the optimal solution for observations it showed that the height determination within 0.033m was available in GNSS Network-RTK positioning.

Comparison of Open Source based Algorithms and Filtering Methods for UAS Image Processing (오픈소스 기반 UAS 영상 재현 알고리즘 및 필터링 기법 비교)

  • Kim, Tae Hee;Lee, Yong Chang
    • Journal of Cadastre & Land InformatiX
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    • v.50 no.2
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    • pp.155-168
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    • 2020
  • Open source is a key growth engine of the 4th industrial revolution, and the continuous development and use of various algorithms for image processing is expected. The purpose of this study is to examine the effectiveness of the UAS image processing open source based algorithm by comparing and analyzing the water reproduction and moving object filtering function and the time required for data processing in 3D reproduction. Five matching algorithms were compared based on recall and processing speed through the 'ANN-Benchmarks' program, and HNSW (Hierarchical Navigable Small World) matching algorithm was judged to be the best. Based on this, 108 algorithms for image processing were constructed by combining each methods of triangulation, point cloud data densification, and surface generation. In addition, the 3D reproduction and data processing time of 108 algorithms for image processing were studied for UAS (Unmanned Aerial System) images of a park adjacent to the sea, and compared and analyzed with the commercial image processing software 'Pix4D Mapper'. As a result of the study, the algorithms that are good in terms of reproducing water and filtering functions of moving objects during 3D reproduction were specified, respectively, and the algorithm with the lowest required time was selected, and the effectiveness of the algorithm was verified by comparing it with the result of 'Pix4D Mapper'.

Design and Analysis of User's Libraries for Parallel Computing based on the Internet (인터넷 기반의 병렬 컴퓨팅을 위한 사용자 라이브러리 설계 및 성능 분석)

  • Sin, Pil-Seop;Jeong, Jun-Mok;Maeng, Hye-Seon;Hong, Won-Gi;Kim, Sin-Deok
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.11
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    • pp.2932-2945
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    • 1999
  • As the Internet and Java technology have been growing up, parallel processing approach to utilize those idle resources connected to the Internet has become quite attractive. In this paper, JICE(Java Internet Computing Environment) was implemented as a parallel computing platform based on the Internet using multithreading and RMI mechanisms provided by Java. The basic model of JICE is constructed as three components, such as a client, a set of workers, and a broker. A worker communicates with other workers via a globally shared memory system. It provides users with master-slave programming model and a collection of library functions. The basic model of JICE is also extended as a multimanaging system. This multimanaging system is evaluated by analysis to show its effectiveness. According to numerical analysis and experiments with several benchmarks, it is shown that the performance of basic model depends on the shared memory reference ratio and user's library is a quite promising.

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Performance Analysis of Multicore Out-of-Order Superscalar Processor with Multiple Basic Block Execution (다중블럭을 실행하는 멀티코어 비순차 수퍼스칼라 프로세서의 성능 분석)

  • Lee, Jong Bok
    • Journal of Korea Multimedia Society
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    • v.16 no.2
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    • pp.198-205
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    • 2013
  • In this paper, the performance of multicore processor architecture is analyzed which utilizes out-of-order superscalar processor core using multiple basic block execution. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the out-of-order superscalar processor with the window size from 32 to 64 and the number of cores between 1 and 16, exploiting multiple basic block execution from 1 to 4 extensively. As a result, the multicore out-of-order superscalar processor with 4 basic block execution achieves 22.0 % average performance increase over the same architecture with the single basic block execution.

An X-Band Carbon-Doped InGaP/GaAs Heterojunction Bipolar Transistor MMIC Oscillator

  • Kim, Young-Gi;Kim, Chang-Woo;Kim, Seong-Il;Min, Byoung-Gue;Lee, Jong-Min;Lee, Kyung-Ho
    • ETRI Journal
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    • v.27 no.1
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    • pp.75-80
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    • 2005
  • This paper addresses a fully-integrated low phase noise X-band oscillator fabricated using a carbon-doped InGaP heterojunction bipolar transistor (HBT) GaAs process with a cutoff frequency of 53.2 GHz and maximum oscillation frequency of 70 GHz. The oscillator circuit consists of a negative resistance generating circuit with a base inductor, a resonating emitter circuit with a microstrip line, and a buffering resistive collector circuit with a tuning diode. The oscillator exhibits 4.33 dBm output power and achieves -127.8 dBc/Hz phase noise at 100 kHz away from a 10.39 GHz oscillating frequency, which benchmarks the lowest reported phase noise achieved for a monolithic X-band oscillator. The oscillator draws a 36 mA current from a 6.19 V supply with 47.1 MHz of frequency tuning range using a 4 V change. It occupies a $0.8mm{\times}0.8mm$ die area.

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EPfuzzer: Improving Hybrid Fuzzing with Hardest-to-reach Branch Prioritization

  • Wang, Yunchao;Wu, Zehui;Wei, Qiang;Wang, Qingxian
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.14 no.9
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    • pp.3885-3906
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    • 2020
  • Hybrid fuzzing which combines fuzzing and concolic execution, has proved its ability to achieve higher code coverage and therefore find more bugs. However, current hybrid fuzzers usually suffer from inefficiency and poor scalability when applied to complex, real-world program testing. We observed that the performance bottleneck is the inefficient cooperation between the fuzzer and concolic executor and the slow symbolic emulation. In this paper, we propose a novel solution named EPfuzzer to improve hybrid fuzzing. EPfuzzer implements two key ideas: 1) only the hardest-to-reach branch will be prioritized for concolic execution to avoid generating uninteresting inputs; and 2) only input bytes relevant to the target branch to be flipped will be symbolized to reduce the overhead of the symbolic emulation. With these optimizations, EPfuzzer can be efficiently targeted to the hardest-to-reach branch. We evaluated EPfuzzer with three sets of programs: five real-world applications and two popular benchmarks (LAVA-M and the Google Fuzzer Test Suite). The evaluation results showed that EPfuzzer was much more efficient and scalable than the state-of-the-art concolic execution engine (QSYM). EPfuzzer was able to find more bugs and achieve better code coverage. In addition, we discovered seven previously unknown security bugs in five real-world programs and reported them to the vendors.

Comparison of Circuit Reduction Techniques for Power Network Noise Analysis

  • Kim, Jin-Wook;Kim, Young-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.4
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    • pp.216-224
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    • 2009
  • The endless scaling down of the semiconductor process made the impact of the power network noise on the performance of the state-of-the-art chip a serious design problem. This paper compares the performances of two popular circuit reduction approaches used to improve the efficiency of power network noise analysis: moment matching-based model order reduction (MOR) and node elimination-based MOR. As the benchmarks, we chose PRIMA and R2Power as the matching-based MOR and the node elimination-based MOR. Experimental results indicate that the accuracy, efficiency, and memory requirement of both methods very strongly depend on the structure of the given circuit, i.e., numbers of the nodes and sources, and the number of moments to preserve for PRIMA. PRIMA has higher accuracy in general, while the error of R2Power is also in the acceptable range. On the other hand, PRIMA has the higher efficiency than R2Power, only when the numbers of nodes and sources are small enough. Otherwise, R2Power clearly outperforms PRIMA in efficiency. In the memory requirement, the memory size of PRIMA increases very quickly as the numbers of nodes, sources, and preserved moments increase.