• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.463-469
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• 2016

This paper presents a compression-friendly low power test scheme in EDT environment. The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. To avoid the impact on encoding efficiency from resulting control data, a counter is utilized to generate control signals. Experimental results obtained for some larger ISCAS'89 and ITC'99 benchmark circuits illustrate that the proposed test application scheme can improve significantly the encoding efficiency of linear decompressor.

• 한국통신학회논문지
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• 제25권4A호
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• pp.558-565
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• 2000

조합형 회로에 대한 테스트 패턴 생성의 문제는 거의 만족할 만한 수준에 도달한데 반해 순차형 회로에 대한 테스트 패턴 생성은 여전히 많은 연구를 필요로 하고 있다. 본 연구에서는 효율적인 검사 패턴 생성을 위하여 검사 패턴 생성 과정에서 탐색되어지는 상태 공간 정보의 효율적으로 저장하고, 그렇게 저장된 상태 공간 정보를 이용하여 효율적으로 검사패턴을 생성하는 알고리즘을 제안한다. 그리고 제안된 알고리즘과 기존의 결정적 검사 패턴 생성 알고리즘을 실험을 통하여 비교함으로써 제안된 알고리즘의 효율성을 검증한다.

• 전자공학회논문지C
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• 제35C권4호
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• pp.30-37
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• 1998

In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.

• ETRI Journal
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• 제28권4호
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.81-88
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• 2002

본 논문에서는 패턴 집단 생성 방식을 사용한 새로운 내장형 자체 테스트를 위한 테스트 패턴 생성기를 제안하였다. 제안된 기술은 클럭당 테스트 환경에서 작은 하드웨어 크기를 가지면서 미리 계산된 결정 테스트 집합을 가진다. 테스트를 제어하기 위한 회로는 간단하여 자동적으로 합성된다. 새로운 패턴 생성기를 기존의 방법들과 비교한 결과를 ISCAS 벤치마크 회로를 가지고 검증하였다.

• 전자공학회논문지A
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• 제32A권12호
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• 전자공학회논문지A
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• 제31A권2호
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• pp.94-103
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• 1994

In testing for practical scan disigned logic circuits, there may exist logic value constraints on some part of primary inputs due to various requirements on design and test. This paper presents a logic value system called taboo logic values which targets the test pattern generation of logic circuits under logic value constraints. The taboo logic system represents the logic value constraints and identifies additional logic value constraints through the implication of the tqaboo logic values using a taboo logic calculus. Those identified logic value constraints will guide the search during the test pattern generation of avoid the unfruitful searches and to identify redundant faults due to the logic value constraints very quickly. Finally, experimental results on ISCAS85 benchmark circuits will demonstrate the efficiency of the taboo logic values.

• 한국소음진동공학회논문집
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• 제24권3호
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• pp.171-179
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• 2014

썬루프 버페팅 현상은 차량 주행시 발생하는 주요 바람소리 문제점 중 하나이다. 버페팅 문제점을 해결하기 위해서 전산 해석을 적용한다면, 실험적 방법보다 비용을 절감할 뿐 아니라 발생 원리 또한 규명할 수 있다. 그러나 전산 해석을 이용하기 위해서는 해석 결과의 정확성이 보장되어야 실제 차량 개발에 적용할 수 있다. 이 연구에서는 해석적 방법의 정확도 향상을 위해 주요 상업용 전산해석 소프트웨어들의 썬루프 버페팅 현상 예측에 대한 벤치마크 테스트를 수행하였다. 해석 대상은 차량의 형상을 간략하게 만든 HSM(Hyundai simplified model)을 이용하였고, 정확도 비교를 위해 속도별 버페팅 현상에 대한 실험을 현대자동차 공력무향풍동에서 실차내부의 흡음재에 의한 효과를 해석적으로 고려하기 위해 음향 응답 실험을 수행하여 해석 결과 정확도 향상을 위해 각 상용 소프트웨어 제작사에 해석 전에 제공 하였다. 이 연구를 통해 대부분의 상용 소프트웨어들이 실험결과와 유사한 해석 결과를 도출하였다. 또한, 실제 차량 개발에서 적용하기 위한 해석 예측 우선순위를 서로 공유하여 추가 해석을 통해 차량 개발에 적용 가능한 보다 정밀한 해석 정확도를 얻어낼 수 있었다.

• Journal of Information Processing Systems
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• 제11권2호
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• pp.229-238
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• 2015

Web shells are programs that are written for a specific purpose in Web scripting languages, such as PHP, ASP, ASP.NET, JSP, PERL-CGI, etc. Web shells provide a means to communicate with the server's operating system via the interpreter of the web scripting languages. Hence, web shells can execute OS specific commands over HTTP. Usually, web attacks by malicious users are made by uploading one of these web shells to compromise the target web servers. Though there have been several approaches to detect such malicious web shells, no standard dataset has been built to compare various web shell detection techniques. In this paper, we present a collection of web shell files, WebSHArk 1.0, as a standard dataset for current and future studies in malicious web shell detection. To provide baseline results for future studies and for the improvement of current tools, we also present some benchmark results by scanning the WebSHArk dataset directory with three web shell scanning tools that are publicly available on the Internet. The WebSHArk 1.0 dataset is only available upon request via email to one of the authors, due to security and legal issues.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.