• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.171.1-171
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• 2001

This paper describes the design and implementation of a new type of a force reflective joystick. It has single degree of freedom that is actuated by motor and brake pair. The use of motor and brake allows various objects to be simulated without the stability problem and related safety issues involved with high torque motors only. The joystick performance is measured by its ability to simulate various test objects. Simple test objects are modeled as a benchmark test of the system´s performance and to evaluate different control approaches for hybrid motor/brake actuator. The force output joystick is capable of simulating forces in a variety of virtual environments. This device demonstrates the effectiveness of a hybrid motor/brake haptic actuator.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.383-386
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• 2000

There are some variations in quiescent supply current or TTL SSIs. Thus, some variations in quiescent supply current of logic circuits made of TTL SSIs will be generated. The variations make it difficult to apply supply current test methods to tests of TTL circuits. In this paper, in order to examine the applicability to R circuits, fault coverages of a supply current test method for open faults in some ISCAS-85 benchmark circuits are evaluated, Which are made of TTL LS-type SSIs. The experimental results shows that if SSIs are used for implementation having the variation of quiescent supply current within 1%, supply current test methods are applicable for the tests.

• Smart Structures and Systems
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• v.15 no.1
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• pp.209-225
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• 2015

Compared to ambient vibration testing, impact testing has the merit to extract not only structural modal parameters but also structural flexibility. Therefore, structural deflections under any static load can be predicted from the identified results of the impact test data. In this article, a signal processing procedure for structural flexibility identification is first presented. Especially, practical issues in applying the proposed procedure for structural flexibility identification are investigated, which include sensitivity analyses of three pre-defined parameters required in the data pre-processing stage to investigate how they affect the accuracy of the identified structural flexibility. Finally, multiple-reference impact test data of a three-span reinforced concrete T-beam bridge are simulated by the FE analysis, and they are used as a benchmark structure to investigate the practical issues in the proposed signal processing procedure for structural flexibility identification.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.41-50
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• 2005

As the size of circuits becomes larger, the test method needs more test data volume and larger test application time. In order to reduce test data volume and test application time, a new test data compression/decompression method is proposed. The proposed method is based on an XOR network uses don't-care-bits to improve compression ratio during seed vectors generation. After seed vectors are produced seed vectors can be merged using two prefix codes. It only requires 1 clock time for reusing merged seed vectors, so test application time can be reduced tremendously. Experimental results on large ISCAS '89 benchmark circuits prove the efficiency of the proposed method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.606-615
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• 1997

This paper proposes an dffcient method for test pattern generation.Current test pattern genration systems generate a test vester for fault $F_{i+l}$ independently of the computation previously done for faults F1,F2...,Fi The proposed algorithm generates a test vector for fault $F_{i+l}$ by inheriting the test vector for fault Fi. A new test vector is grnerated from inherited values by gradually changing the inhderited values .The inherited values may partially activate a fauog and propagate the fault signal,Normally,this reduses the number of decision steps and backtracks in the second search.Experimental results for well-Known benchmark circuts show that the proposed algorithm is very efficient with small backtrack kimit;in combination eith other algorithms,it is very efficient for arbitrary backtrack limits.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.4 no.3
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• pp.227-234
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• 2006

Two candidate glasses, AG8W1 and DG-2, have been developed for vitrifying the mixture of low activity resin, zeolite and Dry Active Waste(DAW), and DAW solely, respectively. In order to evaluate the chemical durability of the glasses, two different leaching tests, Product Consistency Test(PCT) and Vapor Hydration Test(VHT), have been performed. As the results of PCT performed from 7 to 120 days, the leach rates of B, Na, Si and Li in the glasses were much lower than those of the benchmark glass(SRL-EA). As the result of VHT peformed for 7 days, the leach rates were 2 and $10g/m^2/day$ for AG8W1 and DG-2, respectively, The results of VHT met the regulatory guideline( $<50g/m^2/day$) for the low activity glasses of Hanford in the USA. Consequently, two candidate glasses to be used at a commercial operation in the future showed that their chemical durability is satisfactory according to the results of two leaching tests.

• Journal of the Korean Association of Geographic Information Studies
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• v.8 no.3
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• pp.84-95
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• 2005

This paper presents solution heuristics to solving optimal multiple-viewpoint location problems that are based on topographic features. The visibility problem is to maximise the viewshed area for a set of viewpoints on digital elevation models (DEM). For this analysis, five areas are selected, and fundamental topographic features (peak, pass, and pit) are extracted from the DEMs of the study areas. To solve the visibility problem, at first, solution approaches based on the characteristics of the topographic features are explored, and then, a benchmark test is undertaken that solution performances of the solution methods, such as computing times, and visible area sizes, are compared with the performances of traditional spatial heuristics. The feasibility of the solution methods, then, are discussed with the benchmark test results. From the analysis, this paper can conclude that fundamental topographic features based solution methods suggest a new sight of visibility analysis approach which did not discuss in traditional algorithmic approaches. Finally, further research avenues are suggested such as exploring more sophisticated selection process of topographic features related to visibility analysis, exploiting systematic methods to extract topographic features, and robust spatial analytical techniques and optimization techniques that enable to use the topographic features effectively.