• Advances in concrete construction
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• v.4 no.3
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• pp.221-230
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• 2016

This paper presents a preliminary study on the influence of laterite soil replacing conventional fine aggregates on the strength properties of GGBS-blended-concrete. For this purpose, GGBS-blended-concrete samples with 40% GGBS, 60% Portland cement (PC), and locally available laterite soil was used. Laterite soils at 0, 25, 50 and 75% by weight were used in trails to replace the conventional fine aggregates. A control mix using only PC, river sand, course aggregates and water served as bench mark in comparing the performance of the composite concrete mix. Test blocks including 60 cubes for compression test; 20 cylinders for split tensile test; and 20 beams for flexural strength test were prepared in the laboratory. Results showed decreasing trends in strength parameters with increasing laterite content in GGBS-blended-concrete. 25% and 50% laterite replacement showed convincing strength (with small decrease) after 28 day curing, which is about 87-90% and 72-85% respectively in comparison to that achieved by the control mix.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.63-70
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• 1994

In this paper, we propose a fault simulation method based on primary output in combinational circuit. In the deterministic test pattern generation, each test pattern is genterated incrementally. The test pattern is applied to the primary inputs of circuit under test to simulate faults. We detect the faults with respect to each primary output. The fault detection with resptect to each primary output is reflected by the corresponding bit in the detection words, and efficient fault detection for the reconvergent fan-out stem is achieved with dynamic fault propagation. As an experimental result of the fault simulation with our method for the several bench mark circuits, we illustrated the good performance showing that the number of gates to be activated is much reduced as compared with other method which is not based on primary output.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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• 2004.04a
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• pp.3-8
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• 2004

This study describes the validation of the GPS/Levelling using GPS data that were obtained from three Permanent GPS stations of the Jeju island. Each orthometric height of three Permanent GPS stations was calculated from the Bench mark of levelling with Traverse-survey and relative baseline processing The test result shows that the error of closure of orthometric height was about 1.6cm and one of ellipsoidal height was about 1.5cm. This result represents that the geoidal height and undulations are regular in the Jeju island. According to the test results, it is identified that one can calculate the orthometric height using Permanent GPS station data rather than traditional levelling method which has a some complexity especially in Jeju island.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2008-2014
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• 1999

IDDQ testing is an effective testing method to detect various physical defects occurred in CMOS circuits. In this paper, we consider intra-gate shorts within circuit under test and implement IDDQ test pattern generator to find test patterns which detect considered defects. In order to generate test patterns, gate test vectors which detect all intra-gate shorts have to be found by type of gates. Random test sets of 10,000 patterns are applied to circuit under test. If an applied pattern generates a required test vector of any gate, the pattern is saved as an available test pattern. When applied patterns generate all test vectors of all gats or 10,000 patterns are applied to circuit under test, procedure of test pattern generation is terminated. Experimental results for ISCAS'85 bench mark circuits show that its efficiency is more enhanced than that obtained by previously proposed methods.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.82-89
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• 1993

In this paper, we proposed the autonomous algorithm of pseudo-exhaustive testing for the multi-level combinational logic circuits. For the processing of shared-circuit that existed in each cone-circuit when it backtracked the path from PO to PI of CUT at the conventional verification testing, the dependent relation of PI-P0 is presented by a dependence matrix so it easily partitioned the sub-circuits for the pseudo-exhaustive testing. The test pattern of sub-circuit's C-inputs is generated using a binary counter and the test pattern of I-inputs is synthesized using a singular cover and consistency operation. Thus, according to the test patterns presented with the recipe cube, the number of test pattrens are reduced and it is possible to test concurrently each other subcircuits. The proposed algorithm treated CUT's net-list to the source file and was batch processed from the sub-circuit partitioning to the test pattern generation. It is shown that the range of reduced ration of generated pseudo-exhaustive test pattern exhibits from 85.4% to 95.8% when the average PI-dependency of ISACS bench mark circuits is 69.4%.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2000.04a
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• pp.391-398
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• 2000

To evaluate the seismic performance of a base isolated building accurate analytical model should be selected. The analytical results such as reduced accelerations member forces and relative displacements of the superstructure of the base isolated building are only meaningful when the analytical model is close enough to the real structure. Real size one bay-two story steel frame and two kinds of seismic isolators(laminated elastomeric bearing and lead-rubber bearing) are designed. manufactured and constructed in the laboratory. Free vibration tests using fuse bars were conducted to evaluate the change of dynamic characteristics(period and damping) before and after base isolation of the steel frame. The experimental results of free vibration tests were also used as a bench mark for adjusting the selected analytical modeling to real base isolated steel frame.

• International Journal of Aerospace System Engineering
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• v.2 no.2
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• pp.40-43
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• 2015

A hybrid mesh based finite volume compressible flow code (PolySim) has been developed recently. Instead of the simple average method for the gradients of variables at each face, the volume average is applied for the calculation of the viscous flux. What is more, an improved Green Gauss method for the calculation of the gradient is also presented. These two techniques will improve both the accuracy and robustness of the code. The aerodynamic performance of this in-house cell centered code is examined by several widely-used bench-mark test cases. These cases include flows over flat plate and RAE 2822 etc. The comparisons on results between calculation and experiment are conducted. They show that the code can produce good numerical results which agree well with the corresponding experiment data.

• Proceedings of the Korea Concrete Institute Conference
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• 2004.11a
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• pp.671-674
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• 2004

In this study a program 'SAPONC-FRANCE' which is able to evaluate and analysis the elastic behavior property of the domestic FRANCE type containment under pressurization and depressurization in periodic structural integrity test (SIT) was developed. The readings of EAU system that is composed of the pendulum, invar-wire, leveling-pot, bench-mark, thermocouples and acoustic strain gauges were used as input data for operating the program. This program provides the prediction lines and bands of the pressure-strain(or displacement) relationship of concrete due to the changing of inner volume under pressurization and depressurization in SIT of the domestic FRANCE type containment.

• Journal of KIISE:Software and Applications
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• v.34 no.7
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• pp.655-666
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• 2007

Reasoners using typical Tableaux algorithm such as RacerPro, Pellet have a problem in Tableaux algorithm large ABox reasoning. Researches to solve these Problems are dealt with Instance Store of University of Manchester which uses Tableaux algorithm based reasoner and DBMS and KAON2 of University of Karlsruhe using Disjunctive Datalog approach. An evaluation experiment for present reasoners is the experiment of TBox reasoning in most of Tableaux algorithm based one. The most of benchmarking tests in reasoning systems haven't done with ABox reasoning based Tableaux Algorithm but done with TBox reasoning based Tableaux Algorithm. Especially, rarely reported benchmarking tests in reasoners have been issued nowadays. Therefore, this thesis evaluates systems with theory of each reasoners for large ABox reasoning that becomes issues recently with typical reasoners. The large AoBx reasoning engine will be analyzed using Instance Store and KAON2 of Manchester University for large ABox processing. At the analysing method, LUBM(Lehigh University BenchMark), benchmarking test method, and it's test system will be introduced. In conclusion, I recommend appropriate reasoner in various environment with experiment result and characteristic of algorithm used for each reasoner.