• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.778-780
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• 1999

Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.227-233
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• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.636-639
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• 2004

In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

• Journal of Preventive Medicine and Public Health
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• v.46 no.sup1
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• pp.22-27
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• 2013

The purpose of this study was to examine the beneficial effects of a new cognitive intervention program designed for the care and prevention of dementia, namely Learning Therapy. The training program used systematized basic problems in arithmetic and Japanese language as training tasks. In study 1, 16 individuals in the experimental group and 16 in the control group were recruited from a nursing home. In both groups, all individuals were clinically diagnosed with senile dementia of the Alzheimer type. In study 2, we performed a single-blind, randomized controlled trial in our cognitive intervention program of 124 community-dwelling seniors. In both studies, the daily training program using reading and arithmetic tasks was carried out approximately 5 days a week, for 15 to 20 minutes a day in the intervention groups. Neuropsychological measures were determined simultaneously in the groups both prior to and after six months of the intervention. The results of our investigations indicate that our cognitive intervention using reading and arithmetic problems demonstrated a transfer effect and they provide convincing evidence that cognitive training maintains and improves the cognitive functions of dementia patients and healthy seniors.

• Journal of Advanced Navigation Technology
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• v.19 no.6
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• pp.614-622
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• 2015

Binary MQ arithmetic coding is widely used recently as a basic entropy coder in multimedia coding system. MQ coder esteems high in compression efficiency to be used in JBIG2 and JPEG2000. The importance of arithmetic coding is increasing after it is adopted as an unique entropy coder in HEVC standard. In the binary MQ coder, arithmetic approximation without multiplication is used in the process of recursive subdivision of range interval. Because of the MPS/LPS exchange activity happened in MQ coder, output byte tends to increase. This paper proposes an enhanced binary MQ arithmetic coder to make use of a lookup table for AQe using quantization skill in order to reduce the deficiency. Experimental results show that about 4% improvement of compression in case of JBIG2 for bi-level image compression standard. And also, about 1% improvement of compression ratio is obtained in case of lossless JPEG2000 coding. For the lossy JPEG2000 coding, about 1% improvement of PSNR at the same compression ratio. Additionally, computational complexity is not increasing.

• Journal of Elementary Mathematics Education in Korea
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• v.17 no.2
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• pp.185-205
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• 2013

In this study, to begin with, it was discussed to gather vocabularies which are expected to be vocabularies related to four fundamental rules of arithmetic and classify them according to kinds and groups, to demarcate vocabularies related to four fundamental rules of arithmetic for using in elementary school mathematics which are associated with addition, subtraction, multiplication, and division directly. Next, the basic vocabularies related to four fundamental rules of arithmetic were discussed. At this time, regarding vocabularies related addition, subtraction, multiplication, and division as coming from the verb add, subtract, multiply, divide respectively, vocabularies that contains the stem of each verb were considered as the basic vocabularies related to four fundamental rules of arithmetics. Following it, vocabularies which assist the operation and indicate the result of the operation were included, then, vocabularies related to four fundamental rules of arithmetic for using in elementary school mathematics were demarcated and presented according to the following criteria. First, a newly coined verb or derivative using the noun form of a certain verb as a root should not be used. Second, such vocabularies of which examples do not exist or rarely exist in textbooks/workbooks should not be used, even though they are registered in mathematics glossary book published by ministry of education or Korean dictionary published by the national institute of Korean language. Third, vocabularies which are not replaceable and vocabularies which have some didactical reasons for using them should be used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.12
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• pp.2921-2926
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• 2013

In this paper, a decimal floating-point arithmetic unit(DFP) was proposed and redesigned to support high speed arithmetic operation employed parallel processing technique. The basic architecture of the proposed DFP was based on the L.K.Wang's DFP and improved it enabling high speed operation by parallel processing for two operands with same size of exponent. The proposed DFP was synthesized as a target device of xc2vp30-7ff896 using Xilinx ISE and verified by simulation using Flowrian tool of System Centroid co. Compared to L.K.Wang's DFP and reference [6]'s method, the proposed DFP improved data processing speed about 8.4% and 3% respectively in case of same input data.

• Journal of Integrative Natural Science
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• v.1 no.2
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• pp.149-159
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• 2008

We develop two algorithms that nd a minimal polynomial of a finite sequence. One uses Euclid's algorithm, and the other is in essence a minimal polynomial version of the Berlekamp-Massey algorithm. They are formulated naturally and proved algebraically using polynomial arithmetic. They connects up seamlessly with decoding procedure of alternant codes.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.17-25
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• 2008

The differential power attack (DPA)[8] is a very powerful side-channel attack tool against various cryptosystems and the masking method[10] is known to be one of its algorithmic countermeasures. But it is non-trivial to apply the masking method to non-linear functions, especially, to arithmetic adders. This paper proposes simple and efficient masking methods applicable to arithmetic adders. For this purpose, we use the fact that every combinational logic circuit (including the adders) can be decomposed into basic logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT) and try to devise efficient masking circuits for these basic gates. The resulting circuits are then applied to the arithmetic adders to get their masking algorithm. As applications, we applied the proposed masking methods to SEED and SHA-1 in hardware.