• Journal of the Korean Institute of Telematics and Electronics A
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• 제32A권5호
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• ETRI Journal
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• 제33권3호
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• pp.335-343
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• 2011

The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high-speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection-free transmission lines from an on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow-to-wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 ${\Omega}$ for a 50 ${\Omega}$ microstrip and S11 better than -9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 ${\mu}m$ to 940 ${\mu}m$, and substrate thickness changes from 100 ${\mu}m$ to 500 ${\mu}m$.

• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 한국퍼지및지능시스템학회 2005년도 추계학술대회 학술발표 논문집 제15권 제2호
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• pp.515-518
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• 2005

플립칩과 같은 정밀한 전자부품을 일반적인 표면실장방법에 의해 고속으로 장착 시킬 경우에는 칩의 표면이 PCB 실장면에 닿는 순간 접촉력(Contact Force)이 크게 발생한다. 과도한 접촉력에 의해 솔더 볼의 표면에 크랙이 가거나 솔더 볼이 변형되어 좁은 피치 내에서 인접해 있는 솔더 볼이 서로 붙는다든지, 또한 리드가 손상된다든지 하는 등과 같은 현상이 발생하여 표면 실장 불량의 원인이 될 가능성이 높아진다. 또한, 유연한 재질로 구성된 PCB 실장면에 과도한 힘을 가할 시에는 실장면의 국부적인 탄성변형이 발생하여 칩의 장착위치가 변경되어 정확한 위치에의 장착이 어렵게 된다. 따라서 CSP 나 플립 칩과 같은 고정도 칩을 고속으로 정확한 위치에 실장하기 위해서는 칩을 장착할 때 플립칩과 실장면의 자세를 평형상태로 제어할 필요가 있으며, 특히 발생하는 충격을 감소시키기 위한 충격 제어와 충돌 후 일정한 접촉력 유지를 할 수 있는 힘 제어가 필수적임을 알 수 있다. 따라서 본 논문에서는 상기와 같은 자세제어 및 힘제어를 요구하는 플립 칩 장착을 위한 엑츄에이터와 거리/힘 센서 시스템을 개발하였다. 제안된 시스템의 효율성을 입증하기 위해 다양한 환경에서 성능시험을 수행하였으며, 그 결과 제안된 시스템의 만족할 만한 실험결과를 보여주었다.