• ETRI Journal
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• v.19 no.1
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• pp.13-25
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• 1997

In this paper, we propose a new queuing model, MMDP/MMDP/1/K, for an asynchronous transfer mode(ATM) multiplexer with multiple quality of service(QoS) variable bit rate (VBR) traffic in broadband-integrated services digital network (B-ISDN). We use the Markov Modulated Deterministic Process(MMDP) to approximate the actual arrival process and another MMDP for service process Using queuing analysis, we derive a formula for the cell loss probability of the ATM multiplexer in terms of the limiting probabilities of a Markov chain. The cell loss probability can be used for connection admission control in ATM multiplexer and the calculation of equivalent bandwidth for arrival traffic, The major advantages of this approach are simplicity in analysis, accuracy of analysis by comparison of simulation, and numerical stability.

• ETRI Journal
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• v.44 no.2
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• pp.346-354
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• 2022

The SYN flooding attack is widely used in cyber attacks because it paralyzes the network by causing the system and bandwidth resources to be exhausted. This paper proposed a self-information approach for detecting the SYN flooding attack and provided a detection algorithm with a hierarchical policy on a detection time domain. Compared with other detection methods of entropy measurement, the proposed approach is more efficient in detecting the SYN flooding attack, providing low misjudgment, hierarchical detection policy, and low time complexity. Furthermore, we proposed a detection algorithm with limiting system resources. Thus, the time complexity of our approach is only (log n) with lower time complexity and misjudgment rate than other approaches. Therefore, the approach can detect the denial-of-service/distributed denial-of-service attacks and prevent SYN flooding attacks.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.1-8
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• 2011

In this paper, a water tank experiment using Binary Frequency Shift Keying (BFSK) method for text transmission performance by water surface fluctuation is conducted. Water surface fluctuation and delay spread which affect the channel coherence bandwidth is a limiting factor in underwater acoustic communication. The amplitude fluctuation and delay spread the smooth surface and fluctuation surface, were identified. The effective delay spread of both cases are 5ms, 4ms corresponding to the coherence bandwidth of 200Hz, 250Hz, respectively. The bit error rate of BFSK modulated text transmission is about $10^{-4}$ in less than 200bps in smooth surface but less than 250bps in fluctuation surface. Therefore, this experiment shows that the water surface fluctuation is important factor determining the performance of the underwater acoustic transmission.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.5 s.347
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• pp.84-93
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• 2006

Ethernet-PON is an emerging access network technology that provides a low-cost method of deploying optical access lines between OLT and ONUs. It has a point-to-multipoint and multipoint-to-point architecture in downstream and upstream direction, respectively. Therefore, downstream packets are broadcast from an OLT toward all ONUs sithout collision. On the other hand, since alt ONUs share a common channel, the collision may be occurred for the upstream transmission. Therefore, earlier efforts on Ethernet-PON have been concentrated on an upstream MAC protocol to avoid collision. But it is needed to control downstream traffic in practical access network, where the network provider limits available bandwidth according to the number of users. In this paper, we propose a traffic control scheme for supporting the fairness of the downstream bandwidth. The objective of this algorithm is to guarantee the fairness of ONUs while maintaining good performance. In order to do this, we define the service probability that considers the past traffic information for downstream, the number of tokens and the relative size of negotiated bandwidth. We develop the simulation model for Ethernet-PON to evaluate the rate-limiting algorithm by using AWESIM. Some results are evaluated and analyzed in terms of defined fairness factor, delay and dropping rate under various scenario.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.79-85
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• 2009

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

• Journal of Korea Multimedia Society
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• v.13 no.4
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• pp.560-574
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• 2010

Recently, many people can easily contact video telephony service through the mobile terminal owing to the commercialization of 3G communication technology. However, the quality of the serviced video telephony has been not good yet by the actual mobile restrictions. For solving quality problems, this paper presents the design of the object-based video CODEC using hybrid transform in mobile video telephony. The proposed design firstly segment each frame into a significant object and an insignificant object. The proposed design is to improve the quality of a significant object by limiting the bit rate of a insignificant object. Thus, we compress a significant object with high quality and low compression ratio and compress an insignificant object with low quality and high compression ratio. Furthermore, we control the bit rate of the video stream in the limited bandwidth by adjusting the compression ratio of each object. From experimental results, we confirmed that our method has more higher quality than methods in the conventional CODECs at the significant region on the same bit rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.15-20
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• 2012

This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.