• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• Electrical & Electronic Materials
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• v.10 no.1
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• Proceedings of the Korean Geotechical Society Conference
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• 2000.09a
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• pp.9-16
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• 2000

Applicability of the cross shaped drain in a soft clay ground is examined using the laboratory discharge capacity test, column consolidation test and 3-D numerical flow analysis. The equivalent diameter of the tested drains is back-calculated from the laboratory experiment and compared with those calculated from the formula suggested in the literature. The effective range of the cross shaped drain about the discharge capacity and coefficient of permeability is analyzed. The results of numerical analysis show that the cross shaped drain which has a cross-sectional area twice of the band shaped drain can reduce the consolidation time by 30% from that for the band shaped drain in a soft clay ground that K is over 1${\times}$10$\^$-7/cm/sec

• Journal of the Korean Geotechnical Society
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• v.16 no.1
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• pp.43-50
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• 2000

In this paper, the consolidation efficiency and the equivalent diameter of the cross shaped drain are examined by using the laboratory test and the numerical model, and the results are compared with those of the band shaped drain. The equivalent diameter of the tested drains is back-calculated from the laboratory experiment and compared with those calculated from the formula suggested in the literature. The efficiency of the cross shaped drain is evaluated by using the 3-D flow program which was validated by the settlement-time test fill data. The results of laboratory test show that the equivalent diameter of the band shaped drain was close to the Rixner's formula and that of the cross shaped drain was fit to the following formula: $d_w\;=\; \\tarc{3}{4}.(b+t)$The results of the numerical analysis show that the cross shaped drain can reduce the consolidation time by 9-10% from that for the band shaped drain. The equivalent diameter obtained from the numerical flow model by using the field data is 3.5 times smaller than that obtained from the laboratory consolidation test.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.77-87
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• 1993

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.59-64
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• 2016

In this paper, a 10W GaN MMIC was designed and fabricated using the Ku-band SSPA module. For Design and fabrication of the SSPA module using Rogers(RO4003C) substrate was used for Branch-line structure. SSPA modules on budget Divider/Combiner was designed and fabricated less than the maximum insertion loss - 0.7dB. In addition, because it must be applied to the structural nature of GaN MMIC Gate Bias-Drain Bias circuit was implemented to apply the Gate-Drain sequential circuit, implemented the RF Power Detect, Temperature Detect, HPA On/Off function. Design and fabrication Ku-band SSPA Module got the measurement results that satisfy a maximum output of 15.6W, Gain 45.7dB, 19.0% efficiency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.3 s.357
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• pp.1-6
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• 2007

A drain bias switching technique is presented to enhance power added efficiency for WiBro and wireless LAN dual band and dual mode transmitter. Some simulations have been done to predict the effect of drain and gate bias change, and bias switching is proposed to get the higher efficiency for dual mode transmitter which generates different output power for different applications. With drain bias switching and simulated optimum fixed gate bias, the amplifier shows dramatic PAE improvement compared to the amplifier without bias switching. The drain and gate bias switching technique will be useful for multi mode communication system with various functions.

• Proceedings of the Korean Geotechical Society Conference
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• 1999.02a
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• pp.62-70
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• 1999

Artesian pressure exists in Yangsan site, the maximum value of which has been measured as high as 5 t/m$^2$. This paper deals with the prediction of consolidation settlement for the site with artesian pressure. The consolidation settlement at the site has been accelerated using vertical band drains. Since the artesian pressure gives lower effective stress than a static condition, its effect should be considered in the settlement prediction. This case study shows that the prediction of settlement and pore pressure dissipation agrees well with the measurements, when considering the artesian effect.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.160-162
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• 2016

A compact model of tunnel field effect transistor (TFET) has been developed. The model includes a surface potentia calculation module and a band-to-band-tunneling current module. Model comparison with TCAD shows that the mode calculates TFET surface potential and drain current accurately.