• International Journal of Computer Science & Network Security
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• v.21 no.8
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• pp.196-202
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• 2021

DNA sequencing provides fundamental data in genomics, bioinformatics, biology and many other research areas. With the emergent evolution in DNA sequencing technology, a massive amount of genomic data is produced every day, mainly DNA sequences, craving for more storage and bandwidth. Unfortunately, managing, analyzing and specifically storing these large amounts of data become a major scientific challenge for bioinformatics. Those large volumes of data also require a fast transmission, effective storage, superior functionality and provision of quick access to any record. Data storage costs have a considerable proportion of total cost in the formation and analysis of DNA sequences. In particular, there is a need of highly control of disk storage capacity of DNA sequences but the standard compression techniques unsuccessful to compress these sequences. Several specialized techniques were introduced for this purpose. Therefore, to overcome all these above challenges, lossless compression techniques have become necessary. In this paper, it is described a new DNA compression mechanism of pattern matching extended Compression algorithm that read the input sequence as segments and find the matching pattern and store it in a permanent or temporary table based on number of bases. The remaining unmatched sequence is been converted into the binary form and then it is been grouped into binary bits i.e. of seven bits and gain these bits are been converted into an ASCII form. Finally, the proposed algorithm dynamically calculates the compression ratio. Thus the results show that pattern matching extended Compression algorithm outperforms cutting-edge compressors and proves its efficiency in terms of compression ratio regardless of the file size of the data.

• The Journal of Asian Finance, Economics and Business
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• v.8 no.2
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• pp.111-122
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• 2021

The main purpose of the present research is to analyze the effects of trade, financial globalization, and technological progress on income inequality in the Indian economy over the period from 1982 to 2018. For this purpose, the study uses economic growth, financial globalization, trade openness, technological development, and economic inequality variables with appropriate proxies. The study employs the Auto Regressive Distributed Lag (ARDL) approach to co-integration and VECM based Granger causality approach to estimate both the short-run and long-run relationship and causality among variables. Using the ARDL bounds test, the study finds a long-run co-integrating relationship existing among the variables in the model. The study confirms the existence of a positive and significant impact of technological progress on income inequality. Further, globalization's limited impact reflects two offsetting tendencies; trade globalization is associated with a reduction in income inequality, while financial globalization is related to an increase in inequality. The results of VECM based Granger causality approach further confirm that technological progress, trade, and financial globalization causes income inequality both directly and indirectly through economic growth and inflation. In case of India, the results of this research can significantly facilitate stakeholders and policymakers in devising policies towards effective globalization and technological innovation for inclusive growth.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.1
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• pp.65-70
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• 2006

It is hewn that we can apply algebraic attacks on combiners with memory such as summation generators. [1,8] To apply algebraic attacks on combiners with memory, we need to construct algebraic relations between the keystream bits and the initial bits of the LFSRs. Until now, all known methods produce algebraic relations involving several consecutive bits of keystream. [l.4.8] In this paper, we show that algebraic relations involving only one keystream bit can be constructed for summation generators. We also show that there is an algebraic relation involving only one keystream bit for ISG (9) proposed by Lee and Moon. Using this fact, we analyze the keystream generators which generate the keystreams by combining summation generators.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.11
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• pp.4502-4521
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• 2020

At EUROCRYPT 2015, Todo proposed a new technique named division property, and it is a powerful technique to find integral distinguishers. The original division property is also named word-based division property. Later, Todo and Morii once again proposed a new technique named the bit-based division property at FSE 2016 and find more rounds integral distinguisher for SIMON-32. There are two basic approaches currently being adopted in researches under the bit-based division property. One is conventional bit-based division property (CBDP), the other is bit-based division property using three-subset (BDPT). Particularly, BDPT is more powerful than CBDP. In this paper, we use Boolean Satisfiability Problem (SAT)-aided cryptanalysis to search integral distinguishers. We conduct experiments on SIMON-32/-48/-64/-96, SIMON (102)-32/-48/-64, SIMECK-32/-48/-64, LBlock, GIFT and Khudra to prove the efficiency of our method. For SIMON (102)-32/-48/-64, we can determine some bits are odd, while these bits can only be determined as constant in the previous result. For GIFT, more balanced (zero-sum) bits can be found. For LBlock, we can find some other new integral distinguishers. For Khudra, we obtain two 9-round integral distinguishers. For other ciphers, we can find the same integral distinguishers as before.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.13-18
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• 2024

This paper proposes a circuit utilizing auto zero technology to minimize offset and enhance accuracy in the reference generator and comparator. As evidence, a comparison between pre and post auto zero usage revealed a reduction of approximately 90% in standard deviation. The proposed circuit was implemented using a 55nm CMOS process, with an input frequency of 781.2 Hz. It achieves an Effective Number of Bits (ENOB) of 8.01 bits and a Signal-to-Noise Distortion Ratio (SNDR) of 49.98 dB.

• Journal of Korean Tunnelling and Underground Space Association
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• v.17 no.3
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• pp.403-413
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• 2015

This paper presents the cutter bit damage due to the rotation speed of shield TBM cutter head in the mixed ground. The efficient of cutter bits and disk cutter are very important for tunnelling in mixed ground. In particular, this research is focused on the performance of cutter bits during excavation in mixed ground which is consist of the weathered soil and rock formation. In order to carry out this research, the experimental works are prepared performed by using the scaled shield TBM cutter bits evaluation machine developed. The mixed ground is prepared considering with a scale effect of tunnel size. Three different rotation speeds of shield TBM cutter head (i.e. 2, 3, 4 rpm) are applied in the experimental work. The drag forces acting on the cutter bits are measured at each cutter bit during rotation of cutter head. It is also analysed the variation of drag forces due to the rotation speed of shield TBM cutter head. The results of this research are clearly shown that the drag forces acting on the cutter bits are jumped up at the boundary between weathered soil and rock. It is also indicated that the jamping drag forces are increased with increasing the rotation speed of the cutter head. It is found from the research that the higher rotation speed of shield TBM cutter head will be high risk in the mixed ground. It is, therefore, suggested that the use of lower rotation speed of shield TBM cutter head is recommended for reducing the cutter bit damage in practice.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.83-90
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• 2010

Cancelable biometrics is a robust and secure biometric recognition method using revocable biometric template in order to prevent possible compromisation of the original biometric data. In this paper, we present a new cancelable bits extraction method for the facial data. We use our previous cancelable feature template for the bits extraction. The adopted cancelable template is generated from two different original face feature vectors extracted from two different appearance-based approaches. Each element of feature vectors is re-ordered, and the scrambled features are added. With the added feature, biometric bits string is extracted using helper data based method. In this technique, helper data is generated using statistical property of the added feature vector, which can be easily replaced with straightforward revocation. Because, the helper data only utilizes partial information of the added feature, our proposed method is a more secure method than our previous one. The proposed method utilizes the helper data to reduce feature variance within the same individual and increase the distinctiveness of bit strings of different individuals for good recognition performance. For a security evaluation of our proposed method, a scenario in which the system is compromised by an adversary is also considered. In our experiments, we analyze the proposed method with respect to performance and security using the extended YALEB face database

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.274-280
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• 2011

Due to their rapid growth and new paradigm applications, wireless sensor networks(WSNs) are morphing into low power personal area networks(LoWPANs), which are envisioned to grow radically. The fragmentation and reassembly of IP data packet is one of the most important function in the 6LoWPAN based communication between Internet and wireless sensor network. However, since the 6LoWPAN data unit size is 102 byte for IPv6 MTU size is 1200 byte, it increases the number of fragmentation and reassembly. In order to reduce the number of fragmentation and reassembly, this paper presents a new scheme that can be applicable to 6LoWPAN. When a fragmented packet header is constructed, we can have more space for data. This is because we use 8-bits routing table ill instead of 16-bits or 54-bits MAC address to decide the destination node. Analysis shows that our design has roughly 7% or 22% less transmission number of fragmented packets, depending on MAC address size(16-bits or 54-bits), compared with the previously proposed scheme in RFC4944. The reduced fragmented packet transmission means a low power consumption since the packet transmission is the very high power function in wireless sensor networks. Therefore the presented fragmented transmission scheme is well suited for low-power wireless sensor networks.

• Journal of Broadcast Engineering
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• v.22 no.3
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• pp.350-365
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• 2017

Steganography is a technique for secret data communication, which is not perceived by third person between a receiver and a transmitter. It has been developed for thousands of years for the transmission of military, diplomatic or business information. The development of digital media and communication has led to the development of steganography techniques in modern times. Technic of image steganography include the LSB, which fixes the number of embedded bits into a pixel, and PVD, which exploits the difference value in the neighboring pixel pairs. In the case of PVD image steganography, a large amount of information is embedded fluidly by difference value in neighboring pixel pairs and the designed range table. However, since the secret information in order is embedded, if an error of the number of embedded bits occurs in a certain pixel pair, all subsequent information will be destroyed. In this paper, we proposes the method, which improve the vulnerability of PVD property about external attack or various noise and extract secret information. Experimental process is comparison analysis about stego-image, which embedded various noise. PVD shows that it is not possible to preserve secret information at all about noise, but it was possible to robustly extract secret information for partial noise of stego-image in case of the proposed PVD image steganography with locally-fixed number of embedding bits.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.