• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• Journal of Periodontal and Implant Science
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• v.37 no.1
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• pp.65-75
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• 2007

In this study, author examined the effect of the concentration of the inorganic polyphosphate on the process of the bone regeneration by using the 6 weeks old rabbit with the weight of 2.0kg in average. we performed the experiment by using TR-eITFE membrane filled with collagen immersed with 1%, 2%, and 4% of inorganic polyphosphate, respectively, after removing the proper sized cort-ical bones from the calvaria of rabbit. The experimental results were compared with the one of the following four groups: The control group for membrane only, experimental group I for membrane filled with collagen im-mersed with 1% of inorganic polyphosphate, experimental group II for membrane filled with collagen immerse with 2% of inorganic polyphosphate, experimental group III for membrane filled with colla-gen immersed with 4% of inorganic polyphosphate. The fragments of the tissue with membrane were obtained from each group of the sacrificed rab-bits for 4 or 8 weeks sustained after surgery, were then prestained and coated. New bone formation was assessed by histomorphometric and statistical analysis. We may draw the conclusions from these experiments as following: 1. Collagen was an excellent carrier with a minimal inflammatory reaction and sustaining the form. 2. The sample of the 8th week group has shown the best bone regeneration compared with the cases of all groups including the control group. 3. The samples of collagen immersed with 2% and 4% of inorganic polyphosphate have shown more bone regeneration relative to the sample of the 1% inorganic polyphosphate. 4. The new bone regeneration was shown actively in the group for membrane filled with collagen immersed with 4% of inorganic polyphosphate. With above results, it is strongly suggested the use of inorganic polyphosphate with vehicle under TR-eITFE membrane.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1071-1078
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• 2003

In this paper, the planar, compact, and broadband phased array antenna system for IMT-2000 applications has been investigated. Two methods far designing a low-cost and low-complex beam-farming network are proposed. First, a new compact and broadband phase shifter with continuously controlled phase bits is designed by using parallel coupled lines. Second, its equivalent phase delay line is suggested to be capable of replacing the complex phase shifter with a reference phase bit on a phased array antenna. For the purpose of achieving the broadband system, in addition to the broadband phase shifter, a wide-slot antenna with a ground reflector is utilized as an element antenna. Therefore, the phased array antenna system has achieved compact size, broad bandwidth, and wide steering angle, although it has low complexity and low fabrication cost. The 3${\times}$1 phased array antenna system has a compact size of 1.6 λ${\times}$ l.6 λ, which is the sufficient ground plane of the wide-slot antenna. Experimental results present that the S$\_$11/ has less than 15 dB within the band and its radiation patterns on an E-plane have the capability of steering an antenna beam from -29$^{\circ}$to +30$^{\circ}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.31-38
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• 2011

A RAM-based Neural Net is a weightless neural network based on binary neural network. 3-D neural network using this paper is binary neural network with multiful information bits and store counts of training. Recognition method by MRD technique is based on the supervised learning. Therefore neural network by itself can not distinguish between the categories and well-separated categories of training data can achieve only through the performance. In this paper, unsupervised learning algorithm is proposed which is trained existing 3-D neural network without distinction of data, to distinguish between categories depending on the only input training patterns. The training data for proposed unsupervised learning provided by the NIST handwritten digits of MNIST which is consist of 0 to 9 multi-pattern, a randomly materials are used as training patterns. Through experiments, neural network is to determine the number of discriminator which each have an idea of the handwritten digits that can be interpreted.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.41-48
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• 2006

An anti-collision algorithm is very important in the RFID system because it decides tag identification time and tag identification accuracy. We propose improved anti-collision algorithms using Bin slot in RFID system. In the proposed algorithms, if the reader memorizes the Bin slot information, it can reduce the repetition of unnecessary PingID command and the time to identify tags. If we also use ScrollA11ID command in the proposed algorithm, the reader knows the sequence of collided E bits. Using this sequence, the reader can reduce the repetition of PingID command and tag identification time. We analyze the performance of the proposed anti-collision algorithms and compare the performance of the proposed algorithms with that of the conventional algorithm. We also validate analytic results using simulation. According to the analysis, for the random tag n, comparing the proposed algorithms with the conventional algorithm, the performance of the proposed algorithms is about $130\%$ higher when the number of the tags is 200. And for the sequential tag ID, the performance of the conventional algorithm decreases. On the contrary, the performance of the proposed algerian using ScrollA11ID command is about $16\%$ higher than the case of using random tag ID.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.25-31
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• 2009

A low power SRAM using supply voltage charge recycling (SVCR-SRAM) scheme is proposed. It divides into two SRAM cell blocks and supplies two different powers. A supplied power is $V_{DD}$ and $V_{DD}/2$. The other is $V_{DD}/2$ and GND. When N-bit cells are accessed, the charge used in N/2-bit cells with VDD and $V_{DD}/2$ is recycled in the other N/2-bit cells with $V_{DD}/2$ and GND. The SVCR scheme is used in the power consuming parts which bit line, data bus, word line, and SRAM cells to reduce dynamic power. The other parts of SRAM use $V_{DD}$ and GND to achieve high speed. Also, the SVCR-SRAM results in reducing leakage power of SRAM cells due to the body-effect. A 64K-bit SRAM ($8K{\times}8$bits) is implemented in a $0.18{\mu}m$ CMOS process. It saves 57.4% write power and 27.6% read power at $V_{DD}=1.8V$ and f=50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.60-68
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• 2010

In case of sensorineural hearing loss, auditory perception can be activated by electrical stimulation of the nervous system via electrode implanted into the cochlea or auditory nerve. Since the tonotopic map of the human auditory nerve has not been definitively identified, the recording of auditory nerve signal with microelectrode is desirable for determining the tonotopic map. This paper proposes the multi-channel analog front-end for auditory nerve signal detection. A channel of the proposed analog front-end consists of an AC coupling circuit, a low-power 4th-order Gm-C LPF, and a single-slope ADC. The AC coupling circuit transfers only AC signal while it blocks DC signal level. Considering the bandwidth of the auditory signal, the Gm-C LPF is designed with OTAs adopting floating-gate technique. For the channel-parallel ADC structure, the single-slope ADC is used because it occupies the small silicon area. Experimental results shows that the AC coupling circuit and LPF have the bandwidth of 100 Hz - 6.95 kHz and the ADC has the effective resolution of 7.7 bits. The power consumption per a channel is $12\;{\mu}W$, the power supply is 3.0 V, and the core area is $2.6\;mm\;{\times}\;3.7\;mm$. The proposed analog front-end was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.