• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.328-335
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• 2005

bIn this paper, built-in self-repair(BISR) is proposed for semiconductor memories. BISR is consisted of BIST(Buit-in self-test) and BIRU(Built-In Remapping Uint). BIST circuits are required not oがy to detect the presence of faults but also to specify their locations for repair. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. According to the experimental result, we can verify algorithm for replacement of faulty cell.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.85-92
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• 2007

With the development of the memory design and process technology, the production of high-density memory has become a large scale industry. Since these memories require complicated designs and accurate manufacturing processes, It is possible to exist more defects. Therefore, in order to analyze the defects, repair them and fix the problems in the manufacturing process, memory repair using BISR(Built-In Self-Repair) circuit is recently focused. This paper presents an efficient memory BISR architecture that uses spare memories effectively. The proposed BISR architecture utilizes the additional storage space named 'sign bit' for the repair of memories. This shows the better performance compared with the previous works.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.5
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• pp.129-140
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• 2014

BIST(Built-in self test) is to detect various faults of the existing memory and BIRA(Built-in redundancy analysis) is to repair detected faults by allotting spare. Also, BISR(Built-in self repair) which integrates BIST with BIRA, can enhance the whole memory's yield. However, the previous methods were suggested for RAM and are difficult to diagnose disturbance that is NAND-type flash memory's intrinsic fault when used for the NAND-type flash memory with different characteristics from RAM's memory structure. Therefore, this paper suggests a BISD(Built-in self diagnosis) to detect disturbance occurring in the NAND-type flash memory and to diagnose the location of fault, and BISR to repair faulty blocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.73-79
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• 2009

With the advance of VLSI technology, the capacity and density of memories are rapidly growing. In this paper we proposed MRI (Memory built-in self Repair Imagination zone) as reallocation algorithm. All faulty cells of embedded memory are reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.113-120
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper we proposed reallocation algorithm. All faulty cell of embedded memory is reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.237-243
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• 2012

In recent system-on-chip (SoC) designs, several hundred embedded memory cores have occupied the largest portion of the chip area. Therefore, the yield of SoCs is strongly dependent on the yield of the embedded memory cores. If all memories had built-in self repair (BISR) with optimal repair rates, the area overhead would be very large. A bit-map sharing method using a memory grouping is proposed to reduce the area overhead. Since the bit-map memory occupies the largest portion of the area of the built-in redundancy analysis (BIRA), the proposed bit-map sharing method can greatly reduce the area overhead of the BIRA. Based on the experimental results, the proposed method can reduce the area overhead by about 80%.

• Journal of Forest and Environmental Science
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• v.29 no.1
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• pp.15-28
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• 2013

Protected area based ecotourism is now the most interesting topic to the nature lover and policy maker throughout the world because of its linkage with economic benefits, protected area management and biodiversity conservation. Based on this premise our study explores the visitors' perception on the recreational potential of Kaptai National park and its potentiality in ecotourism development in Bangladesh. The field survey was carried out both in holidays and non-holidays of the week from the late winter season in 2009 to the spring season in 2010. A total of 118 visitors were interviewed with the help of a semi-structured questionnaire. Study findings revealed that about 62% male constitute the visitors group with the maximum number of visitors in the age of between 15-25 years (35.59%). The tourists were very much attracted by boat riding (93.22%) followed by scenic beauty of Rampahar-Sitapahar (85.59%). A major portion of about 57.14% tourists wished to visit the park within a year because they got a lot of pleasure from Natural and green environment (86.44%) followed by boating on Kaptai Lake (85.59%). Most of the visitors (36%) were happy about existing facilities but defined some problems such as tour guiding facility, food and drinking water supply, etc. About 71% and 66% respondents perceived that Kaptai National Park made them to be concerned and protective of nature and supports and sustains local ecosystem respectively and 43% respondents agreed that Kaptai National Park ensures the social equity and involve local people in ecotourism which are the most important elements of sustainable ecotourism. The present study results also predict that the park might be a good recreational area for enjoying with family members and group of friends through proper management and promoting the relationships among tourism, local people and biodiversity conservation.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.377-384
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper, We proposed a reallocation algorithm for faulty memory part to efficient reallocation with row and column redundant memory. Reallocation information obtained from faulty memory by only every test. Time overhead problem occurs geting reallocation information as every test. To its avoid, one test resulted from reallocation information can save to flash memory. In this paper, reallocation information increases efficiency using flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.69-81
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• 2008

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.