• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1157-1164
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• 2006

In this paper, we proposed a method for measuring accurate positions and sizes of package and balls in a micro BGA. To find defects of BGA accurately, we focused on finding positions of package and balls. After labeling, we detected connected components of package and balls using feature parameters. After the detection of package component, we measured position and size of package by employing rectangular model which was constructed by the package information. After the detection of the ball components, we measured positions and diameters of balls by employing circular models which were constructed by the ball informations. We did calibration based on landmarks to measure real length, and we compared the measured results with the SEM data. Finally, we found that the accuracy of the proposed method is 94% in terms of ball's radius.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.243-250
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• 2001

This paper presents the structure of a $\mu$Spring package, its fabrication process and an analysis of its electrical characteristics compared to that of a $\mu$BGA. It was found that both $\mu$BGA and $\mu$Spring packages provide with outstanding high speed signal transmission characteristics due to their lower inductance of package interconnection lines, smaller than half of inductance of TSOP package lines. Even the worst case substrate trace of a Rambus DRAM $\mu$Spring package yields the line inductance of 2.9nH, which provides with 25% margin compared to the Rambus DRAM specification of 4nH. The fabrication cost of $\mu$Spring package is lower than that of $\mu$BGA by 50%, passes 1000 thermal cycles, meets JEDEC Level 1 specification whereas $\mu$BGA does not, and thereby yields high reliability and strong competing power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.8-18
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• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of Mechanical Science and Technology
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• v.18 no.2
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• pp.230-239
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• 2004

A compact model approach of a network of spring elements for elastic loading is presented for the thermal deformation analysis of BGA package assembly. High-sensitivity moire interferometry is applied to evaluate and calibrated the model quantitatively. Two ball grid array (BGA) package assemblies are employed for moire experiments. For a package assembly with a small global bending, the spring model can predict the boundary conditions of the critical solder ball excellently well. For a package assembly with a large global bending, however, the relative displacements determined by spring model agree well with that by experiment after accounting for the rigid-body rotation. The shear strain results of the FEM with the input from the calibrated compact spring model agree reasonably well with the experimental data. The results imply that the combined approach of the compact spring model and the local FE analysis is an effective way to predict strains and stresses and to determine solder damage of the critical solder ball.

• Proceedings of the Korean Institute of Industrial Safety Conference
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• 2002.11a
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• pp.305-310
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• 2002

최근 첨단 반도체 패키지 공정에서는 전극형성 공정에 BGA package 시스템이 도입되고 있으며 BGA package은 잔존 flux 및 이물질의 제거공정이 필수적이다. 잔존하는 flux는 세척이 제대로 이루어지지 않을 경우 solder ball들이 고온 또는 습도에 노출되었을 때 lead, circuit board 등의 부식과 conductor Insulation 수축의 원인이 된다.(중략)

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.96-99
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• 2000

We presents a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and examined electrical parameters with a HP5475A TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3 $\times$ 3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, self inductance 146pH, mutual capacitance 10.9fF and mutual inductance 16.9pH. S parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55㎓ and the loss of 0.26dB. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of the Korea Convergence Society
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• v.8 no.11
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• pp.15-20
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• 2017

Recently, with the development of the IT industry, interest in computer convergence technology is increasing in various fields. Especially, in the semiconductor field, a vision system that uses a camera and computer convergence is often used to inspect semiconductor device defects in the production process. Various systems have been studied to remove noise, which is a major cause of degradation in processing of data related to these image processing systems. In this paper, we try to detect defects in BGA (Ball Grid Array) package devices by recognizing defects in advance during mass production. We propose a measurement system using a Gaussian filter, a Median filter, and an Average filter, which are widely used for noise reduction of image data Applying the proposed system to the manufacturing process of the BGA package can be used to judge whether the defect is good or not, and it is expected that productivity will be improved.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.