• Journal of applied mathematics & informatics
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• v.5 no.1
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• pp.99-110
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• 1998

In this paper we study cyclic codes in $Z_m$. i.e., ideals in $Z_mG$, G afinite abelian group and we give a classification of such codes. We also sgtudy the minimum Hamming distance and the generalized Hamming weight of BCH codes over $Z_m$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.1
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• pp.65-74
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• 1989

This paperr presetns the Direct Decoding Method for binary BCH codes which can find the error locattion number directly from the syndrome without calculating the error locator polynomical. Also in this paper, the triple and quadruple error correcting BCH decoder are designed using this method. As an example, the triple error correcting (63.45) BCH decoder is implemented with TTL ICs. It is shown from our results that this decoder can be implemented with relatively simple hardware.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1033-1039
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• 2002

The coding scheme according to service types in AAL2 of ATM-PON is proposed in this paper. The service types and the corresponding error correcting codes are indicated by two of six reserved bits in SSTED of AAL2. Several coding schemes such as BCH and convolutional codes are considered under using the same and different kind of coding schemes. As a result, the (127,120) and (127,106) BCH codes may be the best choice for voice and data service respectively among all the possible schemes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.485-488
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• 2009

The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.374-387
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• 1989

The decoding method of Binary BCH Codes using symmetric matrix is proposed in this paper. With this method, the error-locator-polynomial is composed by symmetric matrix which consists of the powers of the unknown X plus the synfromes as its elements. The symmetric matirx can also be represented in terms of the unknown X. But the each coefficients of the error-locator polynomial represents the matirx with the syndromes as its entries. By utilizing this proposed algorithm, the device for decoding circuit of the (63, 45) BCH Code for t=3 has been implemented for demonstration.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.488-496
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• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.737-745
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• 1999

In this paper, we present encoders and decoders with the two kinds of ternary Bose-Chaudhuri-Hocquenghem(BCH) codes in the most basic ternary code system from among multiple-valued code systems. One is the random-triple-error-correcting ternary BCH(26,14) code for sequential data, the other is random-triple -error-correcting ternary BCH (26,13) code. The encoders and the decoders realized are verified by experiment. Amount of the (26,13) decoder's hardware is about 50% of the one of the (26,14) decoder's one.

• The Journal of the Acoustical Society of Korea
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• v.17 no.7
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• pp.79-81
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• 1998

2진 BCH 부호에 대한 새로운 연판정 복호법을 제안하였다. 후보부호어가 선출되지 않을 때의 성능 저하를 방지할 수 있는 개선된 알고리듬을 개발하여 오정정 확률과 정정 불 능 확률이 낮아지게 하였다. 또한, 복잡도를 줄이는 방안도 개발하여 알고리듬 개선으로 인 한 복잡도 증가가 거의 나타나지 않도록 하였다. (31,16) BCH 부호에 대한 시뮬레이션 결과 로 이러한 사실들을 확인할 수 있었다.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.203-206
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• 1988

Direct Decoding Method for binary BCH codes which directly can find error location number from syndrome without calculating error locator polynomial is presented in this paper. The (255,239) BCH decoder is implemented using TTL logics. It is shown from our results that this decoder can be implemented with relatively simple hardware.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.2
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• pp.156-163
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• 2013

The use of an error-correcting code is essential in communication systems where the channel is noisy. When channel coding parameters are unknown at a receiver side, decoding becomes difficult. To perform decoding without the channel coding information, we should estimate the parameters. In this paper, we introduce a method to reconstruct the generator polynomial of BCH(Bose-Chaudhuri-Hocquenghem) codes based on the idea that the generator polynomial is compose of minimal polynomials and BCH code is cyclic code. We present a probability compensation method to improve the reconstruction performance. This is based on the concept that a random data pattern can also be divisible by a minimal polynomial of the generator polynomial. And we confirm the performance improvement through an intensive computer simulation.