• Title/Summary/Keyword: BCH 부호

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Design of Arithmetic processor with multiple valued BCH code (다치 BCH 부호를 갖는 연산기 설계에 관한 연구)

  • 송홍복;이흥기
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.4
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    • pp.737-745
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    • 1999
  • In this paper, we present encoders and decoders with the two kinds of ternary Bose-Chaudhuri-Hocquenghem(BCH) codes in the most basic ternary code system from among multiple-valued code systems. One is the random-triple-error-correcting ternary BCH(26,14) code for sequential data, the other is random-triple -error-correcting ternary BCH (26,13) code. The encoders and the decoders realized are verified by experiment. Amount of the (26,13) decoder's hardware is about 50% of the one of the (26,14) decoder's one.

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A Direct Decoding Method for Binary BCH Codes (2원 BCH부호의 직접복호법)

  • 염흥렬;이만영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.14 no.1
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    • pp.65-74
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    • 1989
  • This paperr presetns the Direct Decoding Method for binary BCH codes which can find the error locattion number directly from the syndrome without calculating the error locator polynomical. Also in this paper, the triple and quadruple error correcting BCH decoder are designed using this method. As an example, the triple error correcting (63.45) BCH decoder is implemented with TTL ICs. It is shown from our results that this decoder can be implemented with relatively simple hardware.

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FPGA Implementation of BCH Encoder to change code rate (부호율 변경이 가능한 BCH Ecoder의 FPGA구현)

  • Jegal, Dong;Byon, Kun-sik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.05a
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    • pp.485-488
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    • 2009
  • The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.

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Performance of Wireless ATM Cell Transmission with Concatenated Turbo and BCH Coding (터보코드와 BCH코드의 연쇄부호화를 이용한 무선 ATM셀 전송의 성능 분석)

  • 문병현;권광영
    • Journal of Korea Society of Industrial Information Systems
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    • v.7 no.2
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    • pp.1-5
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    • 2002
  • In this paper, a concatenated turbo and BCH coding is proposed for the wireless ATM cell transmission and the bit error rate(BER) and the cell loss ratio(CLR) for the Nosed system is obtained. Turbo code with code rate of 1/2 and BCH code with error correction capability of 5 and 15 bits are used in the simulations. It is shown that the proposed system obtained about 0.2 and 0.4 ㏈ gain over the conventional Turbo code at bit error rate of 0.001. Also the proposed system obtained about 0.1 and 0.2 ㏈ gain over the conventional Turbo code at cell loss rate of 0.01.

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A New Soft-Decision Decoding of Binary BCH Codes (2진 BCH 부호의 새로운 연판정 복호법)

  • 심용걸
    • The Journal of the Acoustical Society of Korea
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    • v.17 no.7
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    • pp.79-81
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    • 1998
  • 2진 BCH 부호에 대한 새로운 연판정 복호법을 제안하였다. 후보부호어가 선출되지 않을 때의 성능 저하를 방지할 수 있는 개선된 알고리듬을 개발하여 오정정 확률과 정정 불 능 확률이 낮아지게 하였다. 또한, 복잡도를 줄이는 방안도 개발하여 알고리듬 개선으로 인 한 복잡도 증가가 거의 나타나지 않도록 하였다. (31,16) BCH 부호에 대한 시뮬레이션 결과 로 이러한 사실들을 확인할 수 있었다.

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Block Turbo Codes applying low generating polynomials for High Code Rate (High Code Rate 달성을 위해 낮은 차수의 생성다항식을 적용한 Block Turbo Codes)

  • Kwon, Kyunghoon;Lee, Donghoon;Heo, Jun
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2011.11a
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    • pp.255-257
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    • 2011
  • 본 논문에서는 지상파 3D HDTV 방송 서비스를 제공하기 위하여 기존의 유럽형 HDTV 방송 서비스인 DVB-T2 전송 시스템의 채널 부호군 중 외부부호로 쓰이는 BCH 부호를 연판정 복호가 가능한 Block Turbo Code로 대체함으로써 생기는 성능 이득과 높은 부호율을 달성하기 위한 방법을 제안하였다. 기존의 DVB-T2 시스템에서 외부부호로 쓰이는 BCH 부호의 부호율의 경우 0.994정도의 높은 부호율을 가진다. 따라서 이에 준하는 높은 부호율을 가지면서 연판정 복호가 가능한 BTC 부호를 제안하고, 기존의 BTC 보다 더 높은 부호율을 가지는 BTC 부호를 설계한다. 모의 실험을 통하여 새롭게 제안된 BTC 에서도 반복복호의 이득이 생기는 것을 확인하고 기존 DVB-T2 시스템의 BCH 부호보다 성능이 우수함을 확인하였다.

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Performance of Coding Scheme for Various Service Types in AAL2 of ATM-PON (ATM-PON의 AAL2에서 서비스 유형별 부호화 방안의 성능)

  • 김우태;배상재;허재두;주언경
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.11C
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    • pp.1033-1039
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    • 2002
  • The coding scheme according to service types in AAL2 of ATM-PON is proposed in this paper. The service types and the corresponding error correcting codes are indicated by two of six reserved bits in SSTED of AAL2. Several coding schemes such as BCH and convolutional codes are considered under using the same and different kind of coding schemes. As a result, the (127,120) and (127,106) BCH codes may be the best choice for voice and data service respectively among all the possible schemes.

The Decoding Algorithm of Binary BCH Codes using Symmetric Matrix (대칭행렬을 이용한 2원 BCH 부호의 복호알고리즘)

  • 염흥렬;이만영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.14 no.4
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    • pp.374-387
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    • 1989
  • The decoding method of Binary BCH Codes using symmetric matrix is proposed in this paper. With this method, the error-locator-polynomial is composed by symmetric matrix which consists of the powers of the unknown X plus the synfromes as its elements. The symmetric matirx can also be represented in terms of the unknown X. But the each coefficients of the error-locator polynomial represents the matirx with the syndromes as its entries. By utilizing this proposed algorithm, the device for decoding circuit of the (63, 45) BCH Code for t=3 has been implemented for demonstration.

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A Modified BCH Code with Synchronization Capability (동기 능력을 보유한 변형된 BCH 부호)

  • Shim, Yong-Geol
    • The KIPS Transactions:PartC
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    • v.11C no.1
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    • pp.109-114
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    • 2004
  • A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

Classification and Generator Polynomial Estimation Method for BCH Codes (BCH 부호 식별 및 생성 파라미터 추정 기법)

  • Lee, Hyun;Park, Cheol-Sun;Lee, Jae-Hwan;Song, Young-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.2
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    • pp.156-163
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    • 2013
  • The use of an error-correcting code is essential in communication systems where the channel is noisy. When channel coding parameters are unknown at a receiver side, decoding becomes difficult. To perform decoding without the channel coding information, we should estimate the parameters. In this paper, we introduce a method to reconstruct the generator polynomial of BCH(Bose-Chaudhuri-Hocquenghem) codes based on the idea that the generator polynomial is compose of minimal polynomials and BCH code is cyclic code. We present a probability compensation method to improve the reconstruction performance. This is based on the concept that a random data pattern can also be divisible by a minimal polynomial of the generator polynomial. And we confirm the performance improvement through an intensive computer simulation.