• Journal of IKEEE
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• v.20 no.4
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• pp.428-431
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• 2016

Power semiconductor devices had been producted with bipolar only processes, but Bipolar-CMOS-DMOS(BCD) processes have been adapted recently to fabricate these devices since most foundry companies have provided BCD processes instead of Bipolar only processes. In this study, Regulator and OP Amp are used as most popular design IPs and BCD processes for the designing are converted from bipolar only processes. Power Switching Sensor(PSS) ICs are designed specifically and fabricated on a silicon chip. The operation results of the packaged chip show the good matching with test results of the simulation.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.477-480
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• 1998

본 연구에서는 정보통신 시스템 민 전자 제어 시스템, atuomobile 저자부문의 핵심부품으로 사용가능한 HV-IC영 BCD 공정 및 소자를 설계하였다. 60V 이상의 bipolr, 20V급 HV-CMOS 소자기술을 one-chip에 구현하는 고내압 BCD 소자구조를 제안, 설계하고 시뮬레이션을 통하여 고안된 소자구조를 검증하여 최적화된 공정 및 소자 변수를 추출하였다.

• Journal of IKEEE
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• v.15 no.1
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• pp.37-42
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• 2011

In this paper, the high-voltage novel devices have been fabricated by 0.35 um BCD (Bipolar-CMOS-DMOS) process. Electrical characteristics of 20 V level BJT device, 30/60 V HV-CMOS, and 40/60 V LDMOS are analyzed. Also, the vertical/lateral BJT with the high-current gain and LIGBT with the high-voltage are proposed. In the experimental results, vertical/lateral BJT has breakdown voltage of 15 V and current gain of 100. The proposed LIGBT with the high-voltage has breakdown voltage of 195 V, threshold voltage of 1.5 V, and Vce, sat of 1.65 V.

• Journal of IKEEE
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• v.28 no.1
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• pp.78-89
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• 2024

PMIC chips based on a BCD process used in automotive semiconductors require multi-time programmable (MTP) intellectual property (IP) that does not require additional masks to trim analog circuits. In this paper, MTP cell size was reduced by about 18.4% by using MTP cells using PMOS capacitors (PCAPs) instead of NMOS capacitors (NCAPs) in MTP cells, which are single poly EEPROM cells with two transistors and one MOS capacitor for small-area MTP IP design. In addition, from the perspective of MTP IP circuit design, the two-stage voltage shifter circuit is applied to the CG drive circuit and TG drive circuit of MTP IP design, and in order to reduce the area of the DC-DC converter circuit, the VPP (=7.75V), VNN (=-7.75V) and VNNL (=-2.5V) charge pump circuits using the charge pumping method are placed separately for each charge pump.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.455-461
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• 2017

In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a $0.13{\mu}m$ BCD is $923.4{\mu}m{\times}1150.96{\mu}m$ ($=1.063mm^2$).

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.463-464
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• 2008

As the demands of LCD and PDP TV are increasing, the high performance HVICs(High Voltage Gate Driver ICs) technology is becoming more necessary. In this paper, we designed the HVIC that has enhanced noise immunity and high driving capability. It can operate at 500KHz switching frequency and permit 600V input voltage. High-side level shifter is designed with noise protection circuit and schmitt trigger. Therefore it has very high dv/dt immunity, the maximum being 50V/ns. The HVIC was designed using $1{\mu}m$ BCD 650V process and verified by Spectre and PSpice of Cadence inc. simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.722-725
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• 2012

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1455-1462
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• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.