• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.6
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• pp.628-636
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• 2022

This paper describes the design of the avionics architecture for military unmanned aerial vehicles considering the airworthiness requirements for the first time. This design considers the redundancy in the system data bus and the power system and the data link system to meet the system safety requirements of the airworthiness requirements of military UAVs. This avionics architecture design has been verified through the system integration test and the flight test after manufacturing the UAV.

• Journal of Advanced Navigation Technology
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• v.26 no.5
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• pp.358-364
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• 2022

The Inter Communication System for avionics is in charge of processing all voice signals that internal calls between Pilot and Co-pilot, internal calls between Pilots and Crews, external calls through communication equipment such as Ultra/Very High Frequency Receiver/Transmitter(U/VHF RT), audio signal monitoring for navigation and mission equipment such as VHF Omnidirectional Range/Instrument Landing System(VOR/ILS), Tactical Air Navigation(TACAN), audio signal output for voice recording to Flight Data Recorder(FDR) and Data Transfer System(DTS), and warning/caution audio signal generate about the status and threat of aircraft. Because Inter Communication System for avionics is sensitive to noise in the case of analog audio signals, a redundant design that can protect audio signal from electromagnetic noise inside/outside of aircraft is required for the mission of pilots and crews. In this paper, Normal/Back-up operation mode and redundancy design plan based on digital method for the redundancy of the digital Inter Communication System for avionics and manufacturing, verification results are described.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.124-131
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• 2014

This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.2
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• pp.213-221
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• 2011

Avionics system tends to be designed to have the integrated architecture, and it is getting difficult and complex to verify the flight-critical function because of sophisticated structure. In Korean Utility Helicopter, mission computer acts as the MUX Bus Controller to handle the data from both communication, identification, mission/display and survivability equipment inside Mission Equipment Package and aircraft subsystems such as fuel system and electrical system while it is interfacing with Automatic Flight Control System and Full-Authority Digital Engine Control via ARINC-429 bus. The Flight Displays which is classified as flight-critical function in aircraft is implemented on Primary Flight Display after mission computer processes data from AFCS in order to generate graphics. This paper defines the flight-critical function implemented in mission computer for KUH, and presents the static and dynamic test procedures which is performed on System Integration Laboratory along with Playback Recorder prior to flight test.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.89-96
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• 2009

As increasing the number of digital control devices installed on aircrafts and their transmission speed, various digital data buses have been introduced to provide reliable and high-speed characteristics. These characteristics of avionics data bus are highly related on the fault-tolerant performance which can make minimize jitter and loss during data transfer. In this paper, we concerned about a new traffic shaping scheme for increasing the reliability of Avionics Full Duplex Switched Ethernet (AFDX) systems based on ARINC 664 standard. We note that the conventional AFDX with a single regulator per virtual link system may produce aggregated traffics as the number of virtual links increasing. The aggregated traffic results in large jitters among frames. To remedy for the jitter and loss of data, we propose a dual regulator scheme for the AFDX system. The purpose of the additional regulator is to additionally regulate aggregated traffics from a number of per virtual link regulators. Using NS-2 simulator, we show that the proposed scheme provides a better performance than the single regulator one. It is worthwhile note that the proposed AFDX with Dual Regulator scheme can be employed to not only aircraft networks but other QoS sensitive networks for robot and industrial control systems.