• Journal of Power Electronics
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• v.17 no.4
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• pp.1117-1126
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• 2017

The main contribution of this paper is the use of sensorless active diodes to generate the gate signals for a three-phase boost-rectifier with a self-powered control scheme. The sensorless operation is achieved making use of the gate control signals generated by the active diode schemes on each of the switching devices using a pulse width half-controlled boost rectifier modulation technique (PWM-HCBR). The proposed scheme synchronizes the gate control signals with a three phase voltage supply. Autonomous operation is obtained making use of the output DC bus to feed the control circuitry, the active diodes and the driver circuitry. The three-phase boost-rectifier is supplied by a three-phase permanent magnet electric generator powered by a solar concentrator dish with variable voltage and variable frequency conditions. Experimental results report an efficiency of up to 94.6% for 25 W and an input of 3.6 V peak per phase with 450.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.325-336
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• 2023

With the development of autonomous driving technology, the number of external contact sensors mounted on vehicles is increasing, and the importance is also rising. The vehicular ultrasonic sensor uses the LIN protocol in the form of a bus topology and reports a status message about its surroundings through the vehicle's internal network. Since ultrasonic sensors are vulnerable to various threats due to poor security protocols, physical testing on actual vehicle is needed. Therefore, this paper developed a LIN-CAN co-analysis testbed with a jig for location-specific distance test to examine the operational relation between LIN and CAN caused by ultrasonic sensors.

• Journal of architectural history
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• v.3 no.1
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• pp.83-99
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• 1994

Ch'ang-Ts'al-Ts'un is a rural Village near Lung-jing City in Yen-pien Korean Autonomous Province of China. It was formed about 100 years ago by Korean Immigrants and has been developed maintaing the characteristics of traditional Korean architecture. Therefore investigating the spatial structure of this village is a meanigful work to confirm and explore one branch of Korean architecture. This study aims at analyzing the spatial structure of the village using direct data collected from the field work and indirect data from books and maps. The field work consists of on-the-site survey of the village layout, interviews of residents, observation notes and photography. Ch'ang-Ts'ai-Ts'un is located 360-370 m high above the sea level and at the side of a long valley. A river flows in the middle of the valley and relatively flat arable land exists at the both sides of the river. The location of the village related to the surrounding river and mountains suggests that the site of the village was chosen according to Feng-Shui, Chinese and Korean traditional architectural theory. The main direction of the house layouts is South-western. The village has been growing gradually until today. Therefore it is meaningful to make the village layout before Liberation(1946 A.D.) because the characteristics of Korean architecture prevailed more in that period. The area of the previous village is limited to the west side of the creek. New houses were later added to the east of the creek, forming a 'New Village'. Previously the village was composed of 3 small villages: Up, Middle and Down. Also the main access roads connecting the village with the neighboring villages were penetrating the village transversely. Presently the main access road comes to the village longitudinally from the main highway located in front of the village. The retrospective layout shows the existence of well-formed Territory, Places and Axes, thus suggesting a coherent Micro-cosmos. The boundary of imaginery territory perceived by present residents could be defined by linking conspicous outside places sorrounding the village such as Five-mountains, Front-mountain, Shin-dong village, Standing-rock, Rear-mountain and Myong-dong village. Inside the territory there are also the important places such as Bus-stop, Memorial tower of patriots, Road-maitenance building and the village itself. And inside it 5 transverse and 1 longitudinal axes exist in the form of river, roads and mountains. The perceived spatial structure of the village formed by Places, Axes and Territory is geometrical and well-balanced and suggests this village is fit for human settlement. The administrative area of the village is about 738 ha, 27 % of which is cultivated land and the rest is mountain area. Initially the village and surrounndings were covered with natural forest But the trees have been gradually cut down for building and warning houses, resulting in the present barren and artificial landscape with bare mountains and cultivated land. At present the area of the village occupied by houses is wedge-shaped, 600 m wide and 220 m deep in its maximum. The total area of the village is $122,175m^{2}$. The area and the rate of each sub-division arc as follow. 116 house-lots $91,465m^{2}$ (74.9 %) Land for public buildings and shops $2,980m^{2}$ (2.4 %) Roads $17,106m^{2}$ (14.0 %) Creek $1,356m^{2}$ (1.1 %) Vacant spaces and others $9,268m^{2}$ (7.6 %) TOTAL $122,175m^{2}$ (100.0 %) Each lot is fenced around with vertical wooden pannels 1.5-1.8 m high and each house is located to the backside of the lot. The open space of a lot is sub-divided into three areas using the same wooden fence: Front yard, Back yard and Access area. Front and back yards are generally used for crop-cultivation, the custom of which is rare in Korea. The number of lots is 116 and the average size of area is $694.7m^{2}$. Outdoor spaces in the village such as roads, vacant spaces, front yard of the cultural hall, front yard of shops and spacse around the creek are good 'behavioral settings' frequently used by residents for play, chatting, drinking and movie-watching. The road system of the village is net-shaped, having T-junctions in intersections. The road could be graded to 4 categories according to their functions: Access roads, Inner trunk roads, Connecting roads and Culs-de-sac. The total length of the road inside the village is 3,709 m and the average width is 4.6 m. The main direction of the road in the village is NNE-SSE and ESE-WNW, crossing with right angles. Conclusively, the spatial structure of Ch'ang-Ts'ai-Ts'un village consists of various components in different dimensions and these components form a coherent structure in each dimension. Therefore the village has a proper spatial structure meaningful and appropriate for human living.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}