• International Journal of Control, Automation, and Systems
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• v.3 no.spc2
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• pp.376-385
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• 2005

The proliferation of technology has made global conduction of business increasingly dependent upon the availability of reliable power. As a result, alternate power systems are being installed and expanded to protect the broadening scope of critical electrical loads. Bus transfer restores designated critical loads to an alternate source when utility derived service becomes inadequate or goes out of service due to any contingency. This paper describes the practices, requirements and implementation of bus transfer of motor loads to an alternate source of power. A new high-speed automatic bus transfer scheme is proposed which includes the development of a new algorithm for determining the type of bus transfer required and the realization of the scheme by using modem protection devices and intra-substation communication facilities.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.137-146
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• 2005

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Interface modules for communication between system buses and IPs are required, since many IPs employ different protocols. Automatic generation of these interface modules would enhance designer's productivity and IP's reusability. This paper proposes an automatic interface generation system based on FSM generated from the protocol description of IPs. The proposed system provides the library modules for the standard buses to reduce the burdens of describing the protocols for data transfer from/to standard buses. Experimental results show that the area of the interface circuits generated by the proposed system had been increased slightly by 4.5% on the average when compared to manual designs. In the experiment, where bus clock is 100 Mhz and slave module clock is 34 Mhz, the latency of the interface had been increased by 7.1% in burst mode to transfer 16 data words. However, occupation of system bus can be reduce by 64.9%. A chip designer can generate an interface that improves the efficiency of system bus, by using this system.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.284-287
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• 1987

In this paper, the design and implementation of a multiprocessor based Die Bonder Machine for the semiconductor will be described. This the partial research result, that is, the 1st year portion of the project to be performed for a period of two years from June, 1986 to May, 1988. The mechanical system consists of the following three subsystems : (i) transfer head unit, (ii) die feeding XY-table unit, and (iii) plunge up unit. The overall control system is designed to be essentially a master-slave type in which each slave is functionally fixed in view of software and also the time shared common bus structure with hardwired bus arbitration scheme is utilized, the control system consists of the following three subsystems each of which employs a 16 bits microprocessor MC 68000 : (i) die bonder processor controller, (ii) visual recognition/inspection and display system, (iii) the servo control system. It is reported that the proposed control system were applied to Working Sample and tested in real system, and the results are successful as a working sample phase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.