• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.415-418
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• 2008

Some embedded microprocessors do not have an FPU(Floating Point Unit) due to a circuit complexity and power consumption. The performance speed of MPEG-4 AAC decoder on this hardware environment would be slower than corresponding speed for playing back of the decoded results. Therefore, irritating and high-pitched noises are interleaved in the original the audio data. So, in order to play MPEG-4 AAC file on such PDA, a new algorithm that transforms floating-point arithmetic to one with integers, is needed. We have developed a transformation algorithm from floating-point operation to integer operation and implemented the PDA's AAC Player. We also show the efficiency of our proposed method with the experimental results.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.180-187
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• 2013

In this paper, we propose a LED communication based multi-hop audio data transmission network system. The main contribution and features of the proposed system are as follows. First, the contribution of this research is to develope the LED communication based multi-hop transmission network system which can transmit audio data signal with long distance via multi-hops. Second, the developed system has the following features: In transmitter, audio data is transmitted after encoding with S/PDIF format via a general LED. The relay receives digital audio signal by using photo diode and then transmits the signal to receiver after error checking and amplifying. The receiver receives the encoded audio data via photo diode and then converts to analog audio signal by using decoding and amplifying. The performance evaluation of the proposed system is conducted in the laboratory with fluorescent light source. The results of the performance evaluation confirm that the system can provide high quality audio transmission from transmiter to receiver via multi-hop relays in a long distance while we can see there are differences in the transmitted audio quality according to the used LED colors.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.21-31
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• 2014

In this paper, we propose VLC(visible light communication) based multi-hop multimedia data transmission system. The main contributions and features of the proposed system are as follows. First, the contribution of this research is to develope the LED communication based multi-hop transmission network system which can transmit multimedia data(audio data, video data) with long distance. Second, the developed system has the following features: In transmitter, audio data and video data are transmitted via multi-hops using two channels. The relay in audio channel receives digital audio signal by using photo diode and then transmits the signal to receiver after error checking and amplifying. The receiver receives the encoded audio data via photo diode and then converts to analog audio signal by using decoding and amplifying. The relay in video channel receives video signal by using photo diode and then amplify the video signal using OP-AMP and then transmits the signal to receiver. The receiver amplifies the received signal from photo diode and then sends it to the monitor. The performance evaluation of the proposed system is conducted in the laboratory with fluorescent light source. The results of the performance evaluation confirm that the system can provide high quality multimedia data transmission from transmiter to receiver via multi-hop relays in a long distance while we can see there are differences in the transmitted multimedia(audio and video) quality according to the used LED colors.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Journal of Internet Computing and Services
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• v.17 no.4
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• pp.11-17
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• 2016

In this paper, we proposed a multi-viewer system with multiple HD cameras based AVB(Audio Video Bridge) ethernet cable using IP networking, and FPGA(Xilinx Zynq 702) for bus safety systems. This AVB (IEEE802.1BA) system can be designed for the low latency based on FPGA, and transmit real-time with HD video and audio signals in a vehicle network. The proposed multi-viewer platform can multiplex H.264 video signals from 4 wide-angle HD cameras with existed ethernet 1Gbps. and 2-wire 100Mbps cables. The design of Zynq 702 based low latency to H.264 AVC CODEC was proposed for the minimization of time-delay in the HD video transmission of car area network, too. And the performance of PSNR(Peak Signal-to-noise-ratio) was analyzed with the reference model JM for encoding and decoding results in H.264 AVC CODEC. These PSNR values can be confirmed according the theoretical and HW result from the signal of H.264 AVC CODEC based on Zynq 702 the multi-viewer with multiple cameras. As a result, proposed AVB multi-viewer platform with multiple cameras can be used for the surveillance of audio and video around a bus for the safety due to the low latency of H.264 AVC CODEC design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.340-343
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• 2005

A realization for digital multimedia receiving system using Conditional Access System is presented in this paper. The key word for descrambling is make from smart card and Conditional Access System, a Stabilization is grow up in the method. It is possible to decoding that of average 15 fame/second of H.264 video format and that 24Khz${\sim}$48Khz audio sample rate using dual processor that of high performance DSP and RISC. This system is evaluated correct descrambling procedure in test stream added that signed user data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.39-44
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• 2009

The advance of communication and networking technology enables high bandwidth multimedia data transmission. The development of high performance compression technology such as H.264 also encourages high quality video and audio data transmission. The trend requires efficient protection system for digital media rights. We propose an efficient digital media protection system using elliptic curve cryptography. Only key parameters are encrypted to reduce the burden of complex encryption and decryption in the proposed system, and the digital media are not played back or the quality is degraded if the encrypted information is missing. We need a playback system with an ECC processor to implement the proposed system. We implement an H.264 decoding system with a configurable ECC processor to verify the proposed protection system We verify that the H.264 movie is not decoded without the decrypted information.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.367-376
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• 2007

In this paper, we introduce an application-specific and adaptive power management technique for portable systems that support dynamic voltage scaling (DVS). We exploit both the idle time of multitasking systems running soft real-time tasks as well as memory- or CPU-bound code regions. Detailed power and execution time profiles guide an adaptive power manager (APM) that is linked to the operating system. A post-pass optimizer marks candidate regions for DVS by inserting calls to the APM. At runtime, the APM monitors the CPU's performance counters to dynamically determine the affinity of the each marked region. for each region, the APM computes the optimal voltage and frequency setting in terms of energy consumption and switches the CPU to that setting during the execution of the region. Idle time is exploited by monitoring system idle time and switching to the energy-wise most economical setting without prolonging execution. We show that our method is most effective for periodic workloads such as video or audio decoding. We have implemented our method in a multitasking operating system (Microsoft Windows CE) running on an Intel XScale-processor. We achieved up to 9% of total system power savings over the standard power management policy that puts the CPU in a low Power mode during idle periods.