• Journal of the Korean Institute of Intelligent Systems
• /
• v.22 no.1
• /
• pp.49-55
• /
• 2012

Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.145-148
• /
• 2000

A 16bit asynchronous multiplier has been designed using micropipelind structure with 2 phase and data bundling. And 4-radix modified Booth algorithm, CPlatch(Cature-Pass latch) and modified 4-2 counters have adopted in this design. It is implemented in 0.65$\mu\textrm{m}$ double-poly/double-metal CMOS technology by using 12,074 transistors with core size of 1.4${\times}$1.8$\textrm{mm}^2$. And our design results in a computation rate 55MHz a supply voltage of 3.3V.

• Journal of Institute of Control, Robotics and Systems
• /
• v.15 no.10
• /
• pp.967-973
• /
• 2009

The model matching problem of asynchronous sequential machines is to design a corrective controller such that the stable-state behavior of the closed-loop system matches that of a prescribed model. In this paper, we address model matching when the external input set consists of controllable inputs and uncontrollable ones. Like in the frame of supervisory control of Discrete-Event Systems (DES), uncontrollable inputs cannot be disabled and must be transmitted to the plant without any change. We postulate necessary and sufficient conditions for the existence of a corrective controller that solves model matching despite the influence of uncontrollable events. Whenever a controller exists, the algorithm for its design is outlined. To illustrate the physical meaning of the proposed problem, the closed-loop system of an asynchronous machine with the proposed control scheme is implemented in VHDL code.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.356-359
• /
• 1999

A high performance 16bit multiplier for asynchronous systems has been designed using asynchronous design methodology. The 4-radix modified Booth algorithm, TSPC (true single phase clocking) registers, and modified 4-2 counters using DPTL (differential pass transistor logic) have been used in our multiplier. It is implemented in 0.65${\mu}{\textrm}{m}$ double-poly/double-metal CMOS technology by using 6616 transistors with core size of 1.4$\times$1.1$\textrm{mm}^2$. And our design results in a computation rate exceeding 60MHz at a supply voltage of 3.3V.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.2
• /
• pp.77-88
• /
• 2009

According to the size of NAND flash memory as the storage system of mobile device becomes large, the performance of address translation and life cycle management in FTL (Flash Translation Layer) to interact with file system becomes very important. In this paper, we propose the continuity counters, which represent the number of continuous physical blocks whose logical addresses are consecutive, to reduce the number of address translation. Furthermore we propose the prefetching method which preloads frequently accessed pages into main memory to enhance I/O performance of flash memory. Besides, we use the 2-bit write prediction and asynchronous writing method to predict addresses repeatedly referenced from host and prevent from writing overhead. The experiments show that the proposed method improves the I/O performance and extends the life cycle of flash memory. As a result, proposed CFTL (Clustered Flash Translation Layer)'s performance of address translation is faster 20% than conventional FTLs. Furthermore, CFTL is reduced about 50% writing time than that of conventional FTLs.