• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.7-11
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• 1998

In this paper, a new synapse cell with nonvolatile SONOS semiconductor memory device is proposed and it's fundamental function electronically implemented SONOS NVSM has shown characteristics that the memory value, synaptic weights, can be increased or decreased incrementally. A novel SONOS synapse is used to read out the stored analog value. For the purpose of synapse implementation using SONOS NVSM, this work has investigated multiplying characteristics including weight updating characteristics and neuron output characteristics. It is concluded that SONOS synapse cell has good agreement for use as a synapse in artificial neural networks.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.475-476
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• 2007

The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhibitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhibitory state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.1-4
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• 1991

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.1-4
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• 1996

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.215-222
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• 2022

Artificial neuromorphic devices are considered the key component in realizing energy-efficient and brain-inspired computing systems. For the artificial neuromorphic devices, various material candidates and device architectures have been reported, including two-dimensional materials, metal-oxide semiconductors, organic semiconductors, and halide perovskite materials. In addition to conventional electrical neuromorphic devices, optoelectronic neuromorphic devices, which operate under a light stimulus, have received significant interest due to their potential advantages such as low power consumption, parallel processing, and high bandwidth. This article reviews the recent progress in optoelectronic neuromorphic devices using various active materials such as two-dimensional materials, metal-oxide semiconductors, organic semiconductors, and halide perovskites

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.5
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• pp.477-481
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• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2977-2979
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• 1999

본 논문에서는 MEBP(Modified Error Back-Propagation) 학습 규칙을 간단한 비선형 회로를 이용하여 구현하였다. 인공 신경 회로망(ANNs : Artificial Neural Networks)은 많은 수의 뉴런을 필요하기 때문에 표준 CMOS 기술을 이용하는 간단한 비선형 시냅스(synapse) 회로는 인공 신경 회로망 구현에 적합하다. 학습회로는 비선형 시냅스 회로. 시그모이드(sigmoid) 회로. 그리고 선형 곱셈기로 구성되어 있다. 학습 회로의 출력은 각 입력 패턴에 따라 유일한 값으로 결정되어진다. 제안한 학술회로를 $2{\times}2{\times}1$과 $2{\times}3{\times}1$ 다층 feedforward 신경 회로망 모델에 적용하였다. MEBP 하드웨어 구현은 HSPICE 회로 시뮬레이터를 이용하여 검증하였다. 제안한 학술 회로는 on-chip 학습회로를 포함한 대규모 신경회로망 구현에 매우 적합하리라 예상된다.

• The Journal of the Korea Contents Association
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• v.18 no.11
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• pp.655-664
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• 2018

Retina transforms the external light into electrical signal that stimulates visual cortex of the brain. Electrical modeling of the retina is useful to understand its structure and action that is a prerequisite to implement the retina as a hardware device. This paper introduces a 2-D electrical network model of vertebrate's retina considering signal pathway of retinal cells and synapses. We implemented a simulator of the retina based on the electrical network model to analyze its operation under various circumstances. Compared to the prior studies, It might contribute designing of artificial retina device in terms of that this study specifically observed input and output reactions of each cell and synapse node under various light intensity on the retina.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.62-74
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• 2023

In response to diverse external stimuli, sensory receptors generate spiking nerve signals. These generated signals are transmitted to the brain along the neural pathway to advance to the stage of recognition or perception, and then they reach the area of discrimination or judgment for remembering, assessing, and processing incoming information. We review research trends in neuromorphic sensory perception technology inspired by biological sensory perception functions. Among the various senses, we consider sensory nerve decoding technology based on sensory nerve pathways focusing on touch and smell, neuromorphic synapse elements that mimic biological neurons and synapses, and neuromorphic processors. Neuromorphic sensory devices, neuromorphic synapses, and artificial sensory memory devices that integrate storage components are being actively studied. However, various problems remain to be solved, such as learning methods to implement cognitive functions beyond simple detection. Considering applications such as virtual reality, medical welfare, neuroscience, and cranial nerve interfaces, neuromorphic sensory recognition technology is expected to be actively developed based on new technologies, including combinatorial neurocognitive cell technology.

• Journal of Adhesion and Interface
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• v.25 no.2
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• pp.43-49
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• 2024

In recent years, the flexible organic synaptic transistor (FOST) has garnered attention for its flexibility, biocompatibility, ease of processability, and reduced complexity, which arise from using organic semiconductors as channel layers. These transistors can emulate the plasticity of the human brain with a simpler structure and lower fabrication costs compared to conventional inorganic synaptic devices. This makes them suitable for applications in next-generation wearable devices and soft robotics technologies. In FOST, the organic substrate is sensitive to the device preparation temperature; high-temperature treatment processes can cause thermal deformation of the organic substrate. Therefore, low-temperature solution-based processing techniques are essential for fabricating high-performance devices. This review summarizes the current research status of low-temperature solution-based FOST devices and presents the problems and challenges that need to be addressed.