• Journal of Industrial Technology
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• v.22 no.B
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• pp.241-249
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• 2002

Optical fiber is indispensable for optical communication systems that transmit large volumes of data at high speed, but super precision technology in sub-micron units is required for optical axis adjustment. We developed the automatic optical fiber by image processing and automatic loading system. we have developed 6-axis micro stage system for I/O optical fiber arrays, the initial automatic aligning system software for a input optical array by the image processing technique, fast I/O-synchronous aligning strategy, the automatic loading/unloading system and the automatic UV bonding mechanism. In order to adjust the alignment it used on PC based motion controller, a $10{\mu}m$ repeat-detailed drawing of automatic loading system is developed by a primary line up for high detailed drawing. Also, at this researches used the image processing system and algorithm instead of the existing a primary hand-line up and fiber input array and waveguide chip formed in line by automatic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.193-197
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• 2013

This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.13-16
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• 1984

This paper proposes a new layout algorithm in order to minimize chip area in one dimensional MOS - LSI composed of basic cells, such as NAND or NOR gates. The virtval gates are constructed, which represent I/O of signal lines at the left-most and at the right-most side of the MCS gate array. With this, a heuristic algorithm is realized that can minimize the number of straight connectors passing through each gate, and as the result, minimize the horizontal tracks necessary to route. The usefulness of the algorithm proposed is shown by the execution of the experimental program on practical logic circuits.

• ETRI Journal
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• v.17 no.2
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• pp.21-30
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• 1995

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.223-227
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• 2003

A new flexible electronic packaging technology and its medical applications are presented. Conventional silicon chips and electronic modules can be considered as "mechanically rigid box." which does not bend due to external forces. This mechanically rigid characteristic prohibits its applications to wearable systems or bio-implantable devices. Using current MEMS (Microelectromechanical Systems) technology. a surface micromachined flexible polysilicon sensor array and flexible electrode array fer neural interface were fabricated. A chemical thinning technique has been developed to realize flexible silicon chip. To combine these techniques will result in a realization of truly flexible sensing modules. which are suitable for many medical applications.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.369-372
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• 2001

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.286-289
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• 2003

In this paper, the performance of W-CDMA system with smart antenna is analyzed for angular spread in spatio-temporal wideband vector channel. We consider correlation between any two elements of antenna array, the angle spread of multipath, and structure of antenna array in this channel model. And each multipath is assumed as a reflective wave from only one direction. Several multipaths within one chip are distinguished into each one and the strongest signal is selected. As a result, the performance of the W-CDMA system with smart antenna in spatio-temporal wideband vector channel has been considerably improved in proportion to the increase of angular spread.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.1
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• pp.73-80
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• 2004

We have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers and GUI are implemented as a system-on-chip for multi-axis motion control. Comparing with the commercial motion controller LM 629, since it has multi-independent PID controllers, we have several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, motion of the robot hand is controlled. The robot hand has three fingers with 2 joints each. Finger movements show that tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.127-135
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• 1994

In this paper we propose an EWLD(Enhanced Weighted Levenshtein Distance) algorithm to organize code-string pattern matching linear array processor based on the mappting to an one-dimensional array from a two-dimensional matching matrix, and design a processing element(PE) of the processor, N PEs are required instead of NS02T in the processor because of the mapping. Data input and output between PEs and all internal operations of each PE are performed in bit-serial fashion. The bit-serial operation consists of the computing of word distance (WD) by comparison and the selection of optimal code transformation path, and takes 22 clocks as a cycle. The layout of a PE is designed based on the double metal $1.5\mu$m CMOS rule. About 1,800 transistors consistute a processing element and 2 PEs are integrated on a 3mm$\times$3mm sized chip.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.727-731
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• 2005

Design and manufacturing process of a full color LED microdislay fabricated by standard CMOS technology and containing an array of aluminum / nanostructured porous silicon reverse biased light emitting Schottky diodes will be discussed. Being of a solid state construction, this microdisplays are cost-effective, thin and light in weight due to very simple device architecture. Its benefits include also super high resolution, wide viewing angles, fast response time and wide operating temperature range. The advantages of full integration of an LED-array and driving circuitry onto a Si-chip will be also discussed.