• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.104-110
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• 1994

We proposed a high speed feature extraction algorithm and developed a feature vector extraction chip for high speed character recognition. It is hard to implement a high speed OCR by software alone with statistical method . Thus, the whole recognition process is divided into functional steps, then pipeline processed so that high speed processing is possible with temporal parallelism of the steps. In this paper we discuss the feature extraction step of the functional steps. To extract feature vector, a character image is normalized to 40$\times$40 pixels. Then, it is divided into 5$\times$5 subregions and 4x4 subregions to construct 41 overlapped subregions(10x10 pixels). It requires to execute more than 500 commands to extract a feature vector of a subregion by software. The proposed algorithm, however, requires only 10 cycles since it can extract a feature vector of a columm of subregion in one cycle with array structure. Thus, it is possible to process 12.000 characters per second with the proposed algorithm. The chip is implemented using EPLD and the effectiveness is proved by developing an OCR using it.

• Design & Manufacturing
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• v.10 no.2
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• pp.50-54
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• 2016

In the semiconductor industry the final products were checked for several environments before sell the products. The burning test of memory and chip was implemented in reliability for all of parts. The memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. In this study, injection molding process analysis was executed for 2 and 4 cavities moldings with runner, gate and sprue. The warpage analysis was also implemented for further gate removal process. Through the analyses the total deformations of the moldings were predicted within maximum 0.05mm deformation. Finally in consideration of these results, 2 and 4 cavities molds were designed and made and tested in injection molding process.

• The Journal of Korean Obstetrics and Gynecology
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• v.20 no.3
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• pp.65-80
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• 2007

Purpose: This study is to examine anti-obesity effect and cytotoxicity of the long-term oral administration of Ephedra Sinica(Ma-hwang, ES) Methods: Using diet-induced obesity C57BL/6 mouse model, anti-obesity effect and DNA chip expression and cytotoxicity of the long-term oral administration of this herbal extract were investigated. Results: The herbal extract treated groups were arrested in weight increment only when they were lodged together. Such effects were abolished when they kept individually. ES fed mice behaved very rudely and violently. On the basis of histological studies of liver tissues and also in vitro cytotoxicity tests of the liver and kidney cell lines, no significant toxicity was found by 14 weeks of ES treatments. However, we found significant changes in gene expression profile in ES treated group by micro-array analysis. In case of ES group, up-regulated genes were 113 and down-regulated were 120. Some of lipid metabolism related genes also significantly changed in treatment groups. Conclusion: ES had effects of increasing the basal metabolic rate by stimulating the sympathetic nervous systems.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.17-25
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• 2006

Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $moir\'{e}$ interferometry. $Moir\'{e}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for both single and double-sided package assemblies are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one because of its symmetric structure. The largest effective strain occurred at the solder ball located on the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one by 50%.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.383-386
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• 2007

In this study, the analysis was carried out for Electrical Discharge Machining (EDM) characteristics of the Cu electrodes by LIGA process. The shape of electrodes has 324 pins for the cavity of BGA(Ball Grid Array) type test socket mold. BGA test sockets are used in the inspection process of the semi-conductor I.C chip manufacturing. In the work, the machining performance for EDM of the electrodes was analyzed on dimensional accuracy and wear rate. The dimensional accuracy was measured for dimension of the pins, pitch size between the pins and the roundness of corner edge using optical measuring machine.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• Journal of information and communication convergence engineering
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• v.15 no.3
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• pp.151-159
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• 2017

Steganography, which is popular as an image processing technology, is the art of using digital images to hide a secret message in such a way that its existence can only be discovered by the sender and the intended receiver. This technique has the advantage of concealing secret information in a cover medium without drawing attention to it, unlike cryptography, which tries to convert data into something messy or meaningless. In this paper, we propose two efficient least significant bit (LSB)-based steganography techniques for designing an image-based steganography system on chip using hardware description language (HDL). The proposed techniques manipulate the LSB plane of the cover image to embed text inside it. The output of these algorithms is a stego-image which has the same quality as that of the original image. We also implement the proposed techniques using the Altera field programmable gate array (FPGA) and Quartus II design software.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1041-1044
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• 1992

A solar cell should be operated at the maximum output point on the I-V characteristic curve with constant current and constant voltage in order that the solar energy be fully utilized. According to, in this paper, we describes a controller which can track the maximum power point of a solar arry using current and voltage ripple variation of step up chopper system. The control circuit is desinged such that actual current and voltage are sensed directly from the solar cell array. These two signal are then holded sampling and multiplies by a single chip multiplier.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1526-1531
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• 2007

Data transmission capacity that is required in 2010 is forecasted that increase by optical communication capacity more than present centuple, and is doing increased demand of optical communication related industry product present. Specially, Lid glass' application that is one of optical communication parts is used in optical communication parts manufacture of Fiber array, Ferrule array, Fanout Black, Silica optical waveguide chip and splitter etc. Also, it is used widely for communication network system, CATV, ATM-PON, FTTH and system. But, Lid glass need much processing times and becomes cause in rising prices of optical communication parts because production cost is expensive. The objectives, of this work is to suggest the micro concave and convex pattern manufacturing technology on borosilicate plate using high temperature and compression molding method. As a result, could developed micro pattern Mold more than 5 pattern, and reduce Lid Glass manufacture cycle time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.561-567
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• 2017

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.