• Title/Summary/Keyword: Array anode

Search Result 25, Processing Time 0.029 seconds

Fabrication of New Co-Silicided Si Field Emitter Array with Long Term Stability (Co-실리사이드를 이용한 새로운 고내구성 실리콘 전계방출소자의 제작)

  • Chang, Gee-Keun;Kim, Min-Young;Jeong, Jin-Cheol
    • Korean Journal of Materials Research
    • /
    • v.10 no.4
    • /
    • pp.301-304
    • /
    • 2000
  • A new triode type Co-silicided Si FEA(field emitter array) was realized by Co-silicidation of Co coated Si FEA and its field emission properties were investigated. The field emission properties of the fabricated device through the unit pixel with $45{\times}45$ tip array in the area of $250{\mu\textrm{m}}{\times}250{\mu\textrm{m}}$ under high vacuum condition of $10^{-8}Torr$ were as follows : the turn-on voltage was about 35V and the anode current was about $1.2\mu\textrm{A}(0.6㎁/tip)$ at the bias of $V_A=500V\;and\; V_G=55V$. The fabricated device showed the stable electrical characteristics without degradation of field emission current for the long term operation except for the initial transient state. The low turn-on voltage and the high current stability of the Co-silicided Si FEA were due to the thermal and chemical stability and the low work function of silicide layer formed at the surface of Si tip.

  • PDF

Current Status of SOFC Materials and Processing Core Technology (고체산화물 연료전지 소재공정 요소기술 개발 현황)

  • Lee, Jong-Ho;Son, Jiwon;Kim, Heryong;Kim, Byong-Kook;Lee, Hae-Weon
    • 한국신재생에너지학회:학술대회논문집
    • /
    • 2010.06a
    • /
    • pp.123.1-123.1
    • /
    • 2010
  • The solid oxide fuel cell (SOFC) has attracted great deal of attention due to its high electrical efficiency, high waste-heat utilization, fuel flexibility, and application versatility. However, SOFC technology is still not matured enough to fulfill the practical requirements for commercialization. Therefore, all the research and development activities are mainly focused on a development of practically viable SOFCs with higher performance and better reliability. We were successful in fabricating high-performance anode-supported unit cells by employing hierarchically controlled multi-layered electrodes for both structural reliability and high performance. In addition, a novel composite sealing gasket made it possible to achieve excellent sealing integrity even with considerable surface irregularities in a multi-cell planar arrayed stack.

  • PDF

Fabrication and Characterization of Si-tip Field Emitter Array (실리콘 팁 전계 방출 소자의 제조 및 동작 특성 평가)

  • 주병권;이상조;박재석;이윤희;전동렬;오명환
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.6 no.1
    • /
    • pp.65-73
    • /
    • 1999
  • Si-tip FEAs were fabricated by a lift-off based process and their operating properties were evaluated. The dependence of emission current on applied gate and anode voltages, maximum emission current, hysteresis phenomena, MOSFET-type curves, current fluctuation, light emission from the emitted electrons, and failure mechanism of the device were widely discussed based on the experimental results.

  • PDF

Fabrication of Sputtered Gated Silicon Field Emitter Arrays with Low Gate Leakage Currents by Using Si Dry Etch

  • Cho, Eou Sik;Kwon, Sang Jik
    • Transactions on Electrical and Electronic Materials
    • /
    • v.14 no.1
    • /
    • pp.28-31
    • /
    • 2013
  • A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

Fabrication of the silicon field emitter araays with H$_{2}$O densified oxide as a gate insulator (H$_{2}$O 분위기에서 치밀화시킨 (densified) 산화막을 게이트 절연막으로 갖는 실리콘 전계방출소자의 제작)

  • 정호련;권상직;이종덕
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.33A no.7
    • /
    • pp.171-175
    • /
    • 1996
  • Gate insulator for Si field emitter is usually formed by e-beam evaporation. However, the evaported oxide requires densification for a stable process and a reduction of gate leakage which results from its Si-rich and nonstoicheiometric structure. In this study, we have developed the process technology able to densify the evaporated oxide in H$_{2}$O ambient. Using this process, we have fabricted thefield emitter array with 625 emitters per pixel, of which gate hole diameter is 1.4.mu.m, for the pixel, anode current of 14.3.mu.A was extracted at a gate bias of 100V and gate leakage was about 0.27% of the total emission current.

  • PDF

Composite Ni-TiO2 nanotube arrays electrode for photo-assisted electrolysis

  • Pozio, Alfonso;Masci, Amedeo;Pasquali, Mauro
    • Advances in Energy Research
    • /
    • v.3 no.1
    • /
    • pp.45-57
    • /
    • 2015
  • This article is addressed to define a new composite electrode constituted by porous nickel and an array of highly ordered $TiO_2$ nanotubes obtained by a previous galvanostatic anodization treatment in an ethylene glycol solution. The electrochemical performances of the composite anode were evaluated in a photo-electrolyser, which showed good solar conversion efficiency with respect to the UV irradiance together with a reduction of energy consumption. Such a combination of materials makes our system simple and able to work both in dark and under solar light exposure, thus opening new perspectives for industrial-scale applications.

Development of Position Encoding Circuit for a Multi-Anode Position Sensitive Photomultiplier Tube (다중양극 위치민감형 광전자증배관을 위한 위치검출회로 개발)

  • Kwon, Sun-Il;Hong, Seong-Jong;Ito, Mikiko;Yoon, Hyun-Suk;Lee, Geon-Song;Sim, Kwang-Souk;Rhee, June-Tak;Lee, Dong-Soo;Lee, Jae-Sung
    • Nuclear Medicine and Molecular Imaging
    • /
    • v.42 no.6
    • /
    • pp.469-477
    • /
    • 2008
  • Purpose: The goal of this paper is to present the design and performance of a position encoding circuit for $16{\times}16$ array of position sensitive multi-anode photomultiplier tube for small animal PET scanners. This circuit which reduces the number of readout channels from 256 to 4 channels is based on a charge division method utilizing a resistor array. Materials and Methods: The position encoding circuit was simulated with PSpice before fabrication. The position encoding circuit reads out the signals from H9500 flat panel PMTs (Hamamatsu Photonics K.K., Japan) on which $1.5{\times}1.5{\times}7.0\;mm^3$ $L_{0.9}GSO$ ($Lu_{1.8}Gd_{0.2}SiO_{5}:Ce$) crystals were mounted. For coincidence detection, two different PET modules were used. One PET module consisted of a $29{\times}29\;L_{0.9}GSO$ crystal layer, and the other PET module two $28{\times}28$ and $29{\times}29\;L_{0.9}GSO$ crystal layers which have relative offsets by half a crystal pitch in x- and y-directions. The crystal mapping algorithm was also developed to identify crystals. Results: Each crystal was clearly visible in flood images. The crystal identification capability was enhanced further by changing the values of resistors near the edge of the resistor array. Energy resolutions of individual crystal were about 11.6%(SD 1.6). The flood images were segmented well with the proposed crystal mapping algorithm. Conclusion: The position encoding circuit resulted in a clear separation of crystals and sufficient energy resolutions with H9500 flat-panel PMT and $L_{0.9}GSO$ crystals. This circuit is good enough for use in small animal PET scanners.

Fabrication of Nanoporous Alumina Membrane by High- Field Anodization (고전계 전기산화에 의한 나노다공성 알루미나 멤브레인의 제조)

  • Kim, Min-Woo;Hyun, Sang-Cheol;Ha, Yoon-Cheol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2010.03b
    • /
    • pp.45-45
    • /
    • 2010
  • Nanoporous anodic alumina membranes (NAAM) with high aspect ratio, self-ordered pore array were fabricated by high-field 2-step anodization method. High voltages of 80, 100, 120 and 140 V as well as 40 V for comparison were applied to an aluminum anode with respect to a Pt cathode immersed both in 0.3M oxalic acid solution in order to investigate the self-ordering characteristics of the nanoporous structure. The pore structures, including interpore distance, pore size, pore density, and porosity as well as the ordering characteristic were analyzed using field-enhanced scanning electron microscopy (FE-SEM) and the corresponding Fourier-transformed images. The nanoporous structure could be produced for all the voltage conditions, but the well-ordered through-hole pore without a branched structure seemed to occur only at 40 and 140 V. It turned out that the growth rate under 140 V high-field anodization was about 40 times higher than under conventional 40 V mild anodization, which enabled the fast fabrication of self-ordered, high aspect ratio NAAMs.

  • PDF

Modeling of High-throughput Uranium Electrorefiner and Validation for Different Electrode Configuration (고효율 우라늄 전해정련장치 모델링 및 전극 구성에 대한 검증)

  • Kim, Young Min;Kim, Dae Young;Yoo, Bung Uk;Jang, Jun Hyuk;Lee, Sung Jai;Park, Sung Bin;Lee, Han soo;Lee, Jong Hyeon
    • Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
    • /
    • v.15 no.4
    • /
    • pp.321-332
    • /
    • 2017
  • In order to build a general model of a high-throughput uranium electrorefining process according to the electrode configuration, numerical analysis was conducted using the COMSOL Multiphysics V5.3 electrodeposition module with Ordinary Differential Equation (ODE) interfaces. The generated model was validated by comparing a current density-potential curve according to the distance between the anode and cathode and the electrode array, using a lab-scale (1kg U/day) multi-electrode electrorefiner made by the Korea Atomic Energy Research Institute (KAERI). The operating temperature was $500^{\circ}C$ and LiCl-KCl eutectic with 3.5wt% $UCl_3$ was used for molten salt. The efficiency of the uranium electrorefining apparatus was improved by lowering the cell potential as the distance between the electrodes decreased and the anode/cathode area ratio increased. This approach will be useful for constructing database for safety design of high throughput spent nuclear fuel electrorefiners.

Ordered Macropores Prepared in p-Type Silicon (P-형 실리콘에 형성된 정렬된 매크로 공극)

  • Kim, Jae-Hyun;Kim, Gang-Phil;Ryu, Hong-Keun;Suh, Hong-Suk;Lee, Jung-Ho
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2008.06a
    • /
    • pp.241-241
    • /
    • 2008
  • Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

  • PDF