• The Journal of Korean Institute of Communications and Information Sciences
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• 제16권12호
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• pp.1236-1248
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• 1991

A new fast algorithm for computing the discrete cosine transform(DCT) Is developed decomposing N-point DCT into an N /2-point DCT and two N /4 point transforms(transpose of an N /4-point DCT. TN/t'and)It has an important characteristic that in this method, the roundoff noise power for a fixed point arithmetic can be reduced significantly with respect to the wellknown fast algorithms of Lee and Chen. since most coefficients for multiplication are distributed at the nodes close to the output and far from the input in the signal flow graph In addition, it also shows three other versions of factorization of DCT matrix with the same number of operations but with the different distributions of multiplication coefficients.

• International Journal of Internet, Broadcasting and Communication
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• 제13권4호
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• pp.39-47
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• 2021

Lempel-Ziv coding is one of the most famous source coding schemes. The output of this source coding is usually a non-uniform code, which requires additional source coding, such as arithmetic coding, to reduce a redundancy. However, this additional source code increases complexity and decoding latency. Thus, this paper proposes the optimal maximum a-posteriori (MAP) receiver for non-uniform source non-orthogonal multiple access (NOMA) with symmetric superposition coding (SSC). First, we derive an analytical expression of the bit-error rate (BER) for non-uniform source NOMA with SSC. Then, Monte Carlo simulations demonstrate that the BER of the optimal MAP receiver for the non-uniform source improves slightly, compared to that of the conventional receiver for the uniform source. Moreover, we also show that the BER of an approximate analytical expression is in a good agreement with the BER of Monte Carlo simulation. As a result, the proposed optimal MAP receiver for non-uniform source could be a promising scheme for NOMA with SSC, to reduce complexity and decoding latency due to additional source coding.

• Communications of the Korean Mathematical Society
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• 제34권4호
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• pp.1105-1115
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• 2019

For positive integers n and k, let $S_k(n)$ and $S^{\prime}_k(n)$ be the sums of the elements in the finite sets {$x^k:1{\leq}x{\leq}n$, (x, n) = 1} and {$x^k:1{\leq}x{\leq}n/2$, (x, n) = 1}respectively. The formulae for both $S_k(n)$ and $S^{\prime}_k(n)$ are established. The explicit formulae when k = 1, 2, 3 are also given.

• Journal of the Korean Society of Systems Engineering
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• 제17권2호
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• pp.37-48
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• 2021

Improving the plant protection system against unforeseen changes/transients during operation is essential to maintain plant safety. Under this condition, it requires rapid and accurate signal processing. The use of an Intellectual Property (IP) core for floating point calculations for Safety Critical MMIS can make numerical computations easier and more precise, improving system accuracy. It can represent and manipulate rational numbers as well as a much broader range of values with dynamic range in nuclear power plant. Systems engineering approach (SE) is used through the development process, it helps to reduce complexity and avoid omissions and invalid assumptions as delivers a better understanding of the stakeholders needs. For the implementation on the FPGA target board, the 32-bit floating-point arithmetic with IEEE-754 standards has designed using Simulink model in Matlab for all operations of addition, subtraction, multiplication and division and VHDL code generated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제41권5호
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• pp.61-70
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• 2004

The operation mode of neural network is divided into learning and recognition process. Learning is updating process of weight until neural network archives target result from input pattern. Recognition is arithmetic process of input pattern and weight. Traditional inner product process is focused to improve processing speed and hardware complexity. There is no hardware architecture to distinguish between loaming and recognition mode of neural network. In this paper we propose the new architecture of low power inner product processor for reconfigurable neural network. The proposed architecture is similar with bit-serial inner product processor on learning mode. It have several advantages which are fast processing base on bit-level, suitability of hardware implementation and pipeline architecture to compute data. And proposed architecture minimizes active units and reduces consumption power on recognition mode. Result of simulation shows that active units is depend on bit representation of weight, but we can reduce active units about 50 precent.

• Journal of the Institute of Electronics and Information Engineers
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• 제49권11호
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of the Institute of Electronics Engineers of Korea TC
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• 제48권6호
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• pp.28-33
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• 2011

Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent user are assigned as '0'. In this paper, based on the fact that there are many '0' input signals in CR systems, a low-power FFT design method for NC-OFDM is proposed. An efficient zero flag generation technique for each stage is first presented. Then, to increase the utility of the zero flag signals, modified architectures for memory and arithmetic circuits are presented. To verify the performance of the proposed algorithm, 2048 point FFT with radix-24SDFstructureisdesignedusingVerilog HDL. The simulation results show that the power consumption of FFT is reduced considerably by the proposed algorithm.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• 제33권4호
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• pp.464-470
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• 2023

Objectives: This study evaluated occupational exposures to noise and heat stress during routine non-outage works in three coal-fired power plants in the Republic of Korea. Methods: The data were collected during the summer of 2020. Full shift noise exposure of 52 workers were measured using noise dosimeters. Heat stress of 16 worksites were measured for 70 minutes using wet-bulb globe temperature monitors. Results: The noise dosimetry results revealed time-weighted averages that ranged from 47.5 to 88.9 dBA. 2 out of 52 noise measurements exceeded 85 dBA. Based on the arithmetic mean, the coal service group showed the highest level at 80.2 dBA by job tasks. Noise exposures exceeding 85 dBA were measured in the coal service and plant operator group. Heat stress index measurements ranged from 20.3℃ to 37.2℃. 1 out of 9 indices measured in coal facilities and 4 out of 7 indices measured in boiler house exceeded 1 hour TWA during moderate work. Heat stress indices measured from boiler houses were significantly higher than those measured from coal equipment. Conclusions: The results show that overexposure to noise and heat stress may be encountered during routine non-outage work activities in coal-fired power plants. Appropriate actions should be taken to reduce future health outcome from occupational exposure to noise and heat stress in the industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권4호
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• pp.94-104
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• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제16권1호
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• pp.143-152
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• 2012

In this paper hardware implementation of GF($2^{191}$) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF($2^m$), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.