• Journal of information and communication convergence engineering
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• v.1 no.3
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• pp.123-128
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• 2003

This paper has addressed the implementation of the single rate Rate Adaptive Shaper(srRAS) described in RFC2963. This shaper has been proposed to use at the ingress of differentiated services networks providing Assured Forwarding Per Hop Behavior (AFPHB). srRAS is typically used in conjunction with single rate Three Color Marker(srTCM) described in RFC2697. srRAS itself is the tail-drop FIFO that is drained at a variable rate, and srTCM is the marker with metering function. G-srRAS is the same as srRAS except that RAS receives the green token state information from the downstream srTCM to avoid delaying a packet in RAS although there are sufficient tokens available to color the packet green. In this paper, we have addressed the algorithm and the architecture of srRAS, and the scheme to implement srRAS using VHDL(Very high-speed integrated circuit Hardware Description Language) and its related tools.

• The KIPS Transactions:PartD
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• v.12D no.6 s.102
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• pp.875-880
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• 2005

Recently web services ale being used to provide environments of distributed computing. Web services provide reusable software component. So, one web service can be used by many users, and one user can use different web services. For reliable use of web services, in these cases, it is important to be fault-tolerance. Existing fault-tolerant methods in web services need a kind of client modification and cannot consider extensible factors like quality. This study suggests the system architecture and description language for the system which can improve some of these problems.

• International Journal of Naval Architecture and Ocean Engineering
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• v.6 no.2
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• pp.392-405
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• 2014

SSPA experiences a growing interest in twin skeg ships as one attractive green ship solution. The twin skeg concept is well proven with obvious advantages for the design of ships with full hull forms, restricted draft or highly loaded propellers. SSPA has conducted extensive hull optimizations studies of LNG ships of different size based on an extensive hull data base with over 7,000 models tested, including over 400 twin skeg hull forms. Main hull dimensions and different hull concepts such as twin skeg and single screw were of main interest in the studies. In the present paper, one twin skeg and one single screw 170 K LNG ship were designed for optimally selected main dimension parameters. The twin skeg hull was further optimized and evaluated using SHIPFLOW FRIENDSHIP design package by performing parameter variation in order to modify the shape and positions of the skegs. The finally optimized models were then built and tested in order to confirm the lower power demand of twin skeg designed compaed with the signle screw design. This paper is a full description of one of the design developments of a LNG twin skeg hull, from early dimensional parameter study, through design optimization phase towards the confirmation by model tests.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.38-43
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• 2006

In this paper, we propose the efficient dead pixel detection algorithm for CMOS image sensors and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However, the presence of the dead pixels degrade the image quality. To detect the dead pixels, the proposed algorithm is composed of scan, trace and detection step. The experimental results showed that it could detect 99.99% of dead pixels. It was designed in a hardware description language and total logic gate count is 3.2k using 0.25 CMOS standard cell library.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.135-139
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• 2009

In this paper we present INCUI, a user interface based on natural view of physical user interface of target devices and services in pervasive computing environment. We present a concept of Intuitively Natural and Consistent User Interface (INCUI) consisted of an image of physical user interface and a description XML file. Then we elaborate how INCUI template can be used to consistently map user interface components structurally and visually. We describe the process of INCUI mapping and a novel mapping method selection architecture based on domain size, types of source and target INCUI. Especially we developed and applied an extended LCS-based algorithm using prefix/postfix/synonym for similarity calculation.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.157-162
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• 2005

Web services are key applications in business­to-business, business-to-customer, and enterprise applications integration solutions. As the mobile internet becomes one of the main methods for information delivery, mobile Web Services are regarded as a critical aspect of e-business architecture. In this paper, we proposed a mobile Web Services middleware that converts conventional internet services into mobile Web services. We implemented a WSDL (Web Service Description Language) builder that converts HTML/XML into WSDL and a SAOP (Simple Object Access Protocol) message processor that performs SOAP message handling, chain and handling of server requests. The former minimizes the overhead cost of rebuilding mobile Web Services and enables seamless services between wired and wireless internet services. The latter enhances SOAP processing performance by eliminating the Servlet container (Tomcat), a required component of typical Web services implementation. Our main contributions are to overcome the latency problem of current Web Services and to provide an easy mobile Web service implementation. Our system can completely support standard Web Services protocol, minimizing communication overhead, message processing time, and server overload. Finally we compare our empirical results with those of typical Web Services.

• Macromolecular Research
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• v.14 no.2
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• pp.140-145
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• 2006

E-science refers to the large-scale science that will increasingly be carried out through distributed global collaborations enabled by the Internet. The Grid is a service-oriented architecture proposed to provide access to very large data collections, very large scale computing resources and remote facilities. Web services, which are server applications, enable online access to service providers. Web portal interfaces can further hide the complexity of accessing facility's services. The main use of synchrotron radiation (SR) facilities by protein crystallographers is to collect the best possible diffraction data for reasonably well defined problems. Significant effort is therefore being made throughout the world to automate SR protein crystallography facilities so scientists can achieve high throughput, even if they are not expert in all the techniques. By applying the above technologies, the e-HTPX project, a distributed computing infrastructure, was designed to help scientists remotely plan, initiate and monitor experiments for protein crystallographic structure determination. A description of both the hardware and control software is given together in this paper.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.99-106
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• 2004

In this Paper, the matched filter for searching initial synchronization in DSSS (direct sequence spread spectrum) receiver is studied. The matched filter with a single data flow path is described which can be presented by HDL (Hardware Description Language). In order to improve the processing time of operations for the filter, equations are arranged to represent two data flow paths and the associated hardware model is proposed. The model has an architecture based on parallelism and pipeline for fast processing, in which two data flow paths with a series of memory, multiplier and accumulator are placed in parallel. The performance of the model is analyzed and compared with the matched filter with a single data flow path.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.43-52
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• 1997

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.