• Journal of Communications and Networks
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• v.7 no.2
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• pp.207-221
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• 2005

The proliferation of wireless local area networks (WLANs) offering high data rate in hot spot area have spurred the demand for possible WLANs and third-generation (3G) cellular network integration solutions as the initiative step towards 4G systems. This paper provides a novel architecture for seamless location-aware integration of WLANs into 3G cellular networks and also an analysis for the efficient handover techniques. We introduce location as a key context in secure roaming mechanism for context-aware interworking in 4G systems. The fast secure roaming with location-aware authentication is implemented at an entity called location-aware service (LAS) broker that utilizes the concepts of direction of user and pre-warming zone. The location-ware interworking architecture supports seamless roaming services among heterogeneous wireless networks including WLANs, wireless metropolitan area networks (WMANs), and 3G cellular networks. This paper also includes a description of procedures needed to implement efficient mobility and location management. We show how the LAS broker with pre-warming and context transfer can obtain significant lower latency in the vertical handover.

• Journal of the Korean Society for Library and Information Science
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• v.48 no.4
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• pp.91-113
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• 2014

Although social metadata has strengths in creating amount of user-contributed resource descriptions, its function is limited because of its non-systematic characteristics. This research proposed an alternative approach to semantic organization of social metadata. It analyzed the semantics of tags created in LibraryThing in order to provide bibliographic categories for describing information resources. Social information Architecture is adopted in generating the bibliographic categories so that social metadata framework can be constructed. This framework can provide the conceptual foundations for semantically organizing social metadata and is expected to be applied to the existing approaches to automatically organize social metadata.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Journal of architectural history
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• v.13 no.4 s.40
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• pp.107-124
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• 2004

The purpose of this study is to understand underlying principle to form the U-type folk house in the northwestern part of Kangwha Island by viewpoint of inner residents. It is found that many factors other than climate are coincidentally affecting the shape of house; Resident's fixed thought like following geomancer' suggestion, seeking fortune, and locating house enclosed low site; Economic reason of uniting one house with two buildings and making small type by used timber from dismantled house; Centralizing life with small courtyard by reason of family type change from extended to nuclear; Influence from L or ㅁ type of upper class building at Seoul area. The method is thick description of culture with ethnographic method from cognitive anthropology: Observing the form and restoring residents' life with open-ended deep interview.

• International Journal of Computer Science & Network Security
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• v.21 no.12
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• pp.9-20
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• 2021

Abstraction applied in computer networking hides network details behind a well-defined representation by building a model that captures an essential aspect of the network system. Two current methods of representation are available, one based on graph theory, where a network node is reduced to a point in a graph, and the other the use of non-methodological iconic depictions such as human heads, walls, towers or computer racks. In this paper, we adopt an abstract representation methodology, the thinging machine (TM), proposed in software engineering to model computer networks. TM defines a single coherent network architecture and topology that is constituted from only five generic actions with two types of arrows. Without loss of generality, this paper applies TM to model the area of network monitoring in packet-mode transmission. Complex network documents are difficult to maintain and are not guaranteed to mirror actual situations. Network monitoring is constant monitoring for and alerting of malfunctions, failures, stoppages or suspicious activities in a network system. Current monitoring systems are built on ad hoc descriptions that lack systemization. The TM model of monitoring presents a theoretical foundation integrated with events and behavior descriptions. To investigate TM modeling's feasibility, we apply it to an existing computer network in a Kuwaiti enterprise to create an integrated network system that includes hardware, software and communication facilities. The final specifications point to TM modeling's viability in the computer networking field.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.37-44
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• 2001

In this paper, an efficient architecture for the ECC multiplier in GF(2") is proposed. We give a design example for the irreducible trinomials $x_{193}\;+\;x_{15}\;+\;1$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. A digit-serial multiplier with a digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The elliptic curve used in this implementation is defined by Weierstrass equations. The measured results show that the proposed multiplier it 0.3 times smaller than the bit-serial LFSR multiplier.lier.

• Korean Journal of Soil Science and Fertilizer
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• v.44 no.5
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• pp.944-958
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• 2011

Soil hydraulic properties such as hydraulic conductivity or water retention which are costly to measure can be indirectly generated by soil pedotransfer function (PTF) using easily obtainable soil data. The field soil structure description which is routinely recorded could also be used in PTF as an input to reduce the uncertainty. The purposes of this study were to use qualitative morphological soil structure descriptions and soil structural index into PTF and to evaluate their contribution in the prediction of soil hydraulic properties. We transformed categorical morphological descriptions of soil structure into quantitative values using categorical principal component analysis (CATPCA). This approach was tested with a large data set from the US National Pedon Characterization database with the aid of a categorical regression tree analysis. Six different PTFs were used to predict the saturated hydraulic conductivity and those results were averaged to quantify the uncertainty. Quantified morphological description was successively used in multiple linear regression approach to predict the averaged ensemble saturated conductivity. The selected stepwise regression model with only the transformed morphological variables and structural index as predictors predicted the $K_{sat}$ with $r^2$ = 0.48 (p = 0.018), indicating the feasibility of CATPCA approach. In a regression tree analysis, soil structure index and soil texture turned out to be important factors in the prediction of the hydraulic properties. Among structural descriptions size class turned out to be an important grouping parameter in the regression tree. Bulk density, clay content, W33 and structural index explained clusters selected by a two step clustering technique, implying the morphologically described soil structural features are closely related to soil physical as well as hydraulic properties. Although this study provided relatively new method which related soil structure description to soil structure index, the same approach should be tested using a datasets containing the actual measurement of hydraulic properties. More insight on the predictive power of soil structure index to estimate hydraulic properties would be achieved by considering measured the saturated hydraulic conductivity and the soil water retention.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.328-335
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• 2010

In this paper, an efficient algorithm and area-efficient hardware architecture have been proposed for $2{\times}2$ MIMO-OFDM based WLAN baseband modem with two transmit and two receive antennas. To enhance the performance of the receiver, the efficient timing synchronization algorithm and symbol detector based on MML algorithm are presented. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate, the complexity of the proposed architecture is dramatically decreased. The proposed area-efficient hardware design was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. As a result, the complexity of the proposed modem receiver is reduced by 56% over the conventional architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.41-50
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• 2010

In this paper, an area-efficient symbol detector is proposed for MIMO communication systems with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate，the complexity of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of logic slices for the proposed symbol detection is 52490 and the number of DSP48s (dedicated multiplier) is 52, which are reduced by 35.3% and 85.3%, respectively, compared with the conventional architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.