• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1858-1864
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• 2009

In this paper, we design a non-volatile memory IP, 1-kb one-time programmable (OTP) memory, used for power management ICs. Since a conventional OTP cell uses an isolated NMOS transistor as an antifuse, there is an advantage of it big cell size with the BCD process. We use, therefore, a PMOS transistor as an antifuse in lieu of the isolated NMOS transistor and minimize the cell size by optimizing the size of a OTP cell transistor. And we add an ESD protection circuit to the OTP core circuit to prevent an arbitrary cell from being programmed by a high voltage between the terminals of the PMOS antifuse when the ESD test is done. Furthermore, we propose a method of turning on a PMOS pull-up transistor of high impedance to eliminate a gate coupling noise in reading a non-programmed cell. The layout size of the designed 1-kb PMOS-type antifuse OTP IP with Dongbu's $0.18{\mu}m$ BCD is $129.93{\times}452.26{\mu}m^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.84-87
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• 2010

We manufacture an antifuse OTP (One-time programmable) cell for analog trimming which will be used in power management ICs. For the antifuse cell using dual program voltage of VPP (=7V) and VNN (=-5V), the thin gate oxide is broken down by applying a voltage higher than the hard break-down voltage to the terminals of the antifuse. The area of the manufactured antifuse OTP cell using $0.18{\mu}m$ BCD process is $48.01{\mu}m^2$ and is about 44.6 percent of that of an eFuse cell. The post-program resistances of the antifuse are good with the values under several kilo ohms when we measure twenty test patterns.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.106-109
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• 2004

A high-density 3-transistor cell one-time programmable (OTP) ROM array using standard CMOS Gate-Oxide antifuse (AF) is proposed, fabricated, and characterized with $0.18{\mu}m$ CMOS process. The proposed non-volatile high-density OTP ROM is composed of an array of 3-T OTP cells with the 3-T consisting of an nMOS AF, a high voltage (HV) blocking transistor, and a cell access transistor, all compatible with standard CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.