• Journal of the Korean Society for Heat Treatment
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• v.14 no.3
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• pp.160-166
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• 2001

The change of ribbon geometry, microstructure and shape recovery with Mn contents, wheel speed and various annealing temperature have been studied in Fe-X%Mn-5Cr-5Co-4Si (X%=15, 20, 24) shape memory alloy (SMA) ribbons rapidly solidfied by single roll chill-block melt-spinning process. The thickness and width of melt-spun ribbons are reduced, results in refining and uniformalizing grains with increasing wheel speed. In the ribbons melt-spun at a wheel speed of 15m/sec, both ${\varepsilon}$ and ${\alpha}^{\prime}$martensites are formed in ribbon 1 (15.5wt%Mn), while only ${\varepsilon}$ martensite is revealed in ribbon 2 (20.2wt%Mn) and ribbon 3 (23.5wt%Mn). The volume fraction of ${\varepsilon}$ martensite is decreased with increasing Mn contents, and those of ${\varepsilon}$ as well ${\alpha}^{\prime}$martensites are increased due to thermal stress relief and grain growth with increasing annealing temperature. Ms temperatures of the ribbons 1, 2 and 3 are fallen with increasing Mn contents. $M_s$ temperatures of the ribbons 1, 2 and 3 annealed at $300^{\circ}C$ for 3 min are risen abruptly, but are nearly constant even at higher annealing temperature, i.e., 400, 500 and $600^{\circ}C$ for 3 min. Shape recovery of the ribbons 1, 2 and 3 increased 30%, 52% and 69% with Mn contents, respectively. Shape recovery of ribbon 1 (15.5wt%Mn) formed ${\varepsilon}$ and ${\alpha}^{\prime}$martensites decreased because of the presence of ${\alpha}^{\prime}$martensite but those of ribbon 2 (20.2wt%Mn) and ribbon 3 (23.5wt%Mn) formed ${\varepsilon}$ martensite increased with increasing annealing temperature.

• Journal of the Korean Vacuum Society
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• v.22 no.5
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• pp.245-249
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• 2013

The $HfO_X$ thin film was deposited what it has been paid attention to the next generation oxide thin layer of MOSFET (metal-Oxide semiconductor field-effect-transistor) by rf magnetron sputter on Si (100) substrate. The $HfO_X$ thin film was deposited using a various oxygen gas flows (5, 10, 15 sccm). After deposition, $HfO_X$ thin films were annealed from 400 to $800^{\circ}C$ for 20 min in nitrogen ambient. The electrical characteristics of the $HfO_X$ thin film was improved by leakage current properties, depending on the increase of oxygen gas flow and annealing temperature. In particular, the properties of nano-mechanics of $HfO_X$ thin films were measured by AFM and Nano-indenter. From the results, the maximum indentation depth at the basis of maximum indentation force was increased from 24.9 to 38.8 nm according to increase the annealing temperature. Especially, the indentation depth was increased rapidly at $800^{\circ}C$. The rapid increasement of indentation depth was expected to be due to the change of residual stress in the $HfO_X$ thin film, and this result was caused by relative flux of oxygen outgasing during the annealing process.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.1-5
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• 2006

We prepared 80 nm-thick TiSix on each 70 nm-thick amorphous silicon and polysilicon substrate using an RF sputtering with $TiSi_2$ target. TiSix composite silicide layers were stabilized by rapid thermal annealing(RTA) of $800^{\circ}C$ for 20 seconds. Line width of $0.5{\mu}m$ patterns were embodied by photolithography and dry etching process, then each additional annealing process at $750^{\circ}C\;and\;850^{\circ}C$ for 3 hours was executed. We investigated the change of sheet resistance with a four-point probe, and cross sectional microstructure with a field emission scanning electron microscope(FE-SEM) and transmission electron microscope(TEM), respectively. We observe an abrupt change of resistivity and voids at the silicide surface due to interdiffusion of silicide and composite titanium silicide in the amorphous substrates with additional $850^{\circ}C$ annealing. Our result implies that the electrical resistance of composite titanium silicide may be tunned by employing appropriate substrates and annealing condition.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.9
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• pp.536-542
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• 2018

Tin dioxide, $SnO_2$, is a well-known n-type semiconductor that shows change in resistance in the presence of gas molecules, such as $H_2$, CO, and $CO_2$. Considerable research has been done on $SnO_2$ semiconductors for gas sensor applications due to their noble property. The nanomaterials exhibit a high surface to volume ratio, which means it has an advantage in the sensing of gas molecules. In this study, SnO nanoplatelets were grown densely on Si substrates using a thermal CVD process. The SnO nanostructures grown by the vapor transport method were post annealed to a $SnO_2$ phase by thermal CVD in an oxygen atmosphere at $830^{\circ}C$ and $1030^{\circ}C$. The pressure of the furnace chamber was maintained at 4.2 Torr. The crystallographic properties of the post-annealed SnO nanostructures were investigated by Raman spectroscopy and XRD. The change in morphology was confirmed by scanning electron microscopy. As a result, the SnO nanostructures were transformed to a $SnO_2$ phase by a post-annealing process.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.3 no.4
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• pp.301-307
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• 2005

The morphology of the high burnup $UO_2$ spent fuel, which was oxidized and annealed in a PIA (Post Irradiation Annealing) apparatus, has been observed. The high burnup fuel irradiated in Ulchin Unit 2, average rod burnup 57,000 MWd/tU, was transported to the KAERI's PIEF. The test specimen was used with about 200 mg of the spent $UO_2$ fuel fragment of the local burnup 65,000 MWd/tU. This specimen was annealed at $1400^{\circ}C$ for 4hrs after the oxidation for 3hrs to grain boundary using the PIA apparatus in a hot-cell. In order to oxidize the grain boundary, the oxidation temperature increased up to $500^{\circ}C$ and held for 3hrs in the mixed gas (60 ml He and 100 ml STD-air) atmosphere. The amount of 85Kr during the whole test process was measured to know the fission gas release behavior using the online system of a beta counter and a gamma counter. The detailed micro-structure was observed by a SEM to confirm the change of the fuel morphology after this test. As the annealing temperature increased, the fission products were observed to move to the grain surface and grain boundary of the $UO_2$ matrix. This specimen was re-structured through the reduction process, and the grain sizes were distributed from 5 to $10\;{\mu}m$.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Polymer(Korea)
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• v.36 no.2
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• pp.131-136
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• 2012

Residual stress is developed in the injection molded articles during the molding process due to temperature variation and shear stress. The residual stress causes the deformation and warpage in the injection molded parts shortly within several days or after several years. Therefore, the injection molding conditions should be optimized to reduce the residual stress. And residual stress in the part should be also relaxed after molding process to maintain its shape. According to the annealing conditions, such as relative humidity, temperature and time, this study investigates the relaxation of residual stress generated in the transparent injection molded specimens. Through the experimental results, it was realized that the residual stress was relaxed at a relative humidity higher than 50%. Utilizing photoelasticity equipment, it was found that the residual stress was rapidly relaxed near glass transition temperature. Additionally, we recognized that the specimen shrunk along the flow direction but expanded to the perpendicular direction of the flow during the annealing processes, which resulted in the warpage of the specimen.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.288-289
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• 2011

Indium Tin Oxide (ITO) is a typical highly Transparent Conductive Oxide (TCO) currently used as a transparent electrode material. Most widely used deposition method is the sputtering process for ITO film deposition because it has a high deposition rate, allows accurate control of the film thickness and easy deposition process and high electrical/optical properties. However, to apply high quality ITO thin film in a flexible microelectronic device using a plastic substrate, conventional DC magnetron sputtering (DMS) processed ITO thin film is not suitable because it needs a high temperature thermal annealing process to obtain high optical transmittance and low resistivity, while the generally plastic substrates has low glass transition temperatures. In the room temperature sputtering process, the electrical property degradation of ITO thin film is caused by negative oxygen ions effect. This high energy negative oxygen ions(about over 100eV) can be critical physical bombardment damages against the formation of the ITO thin film, and this damage does not recover in the room temperature process that does not offer thermal annealing. Hence new ITO deposition process that can provide the high electrical/optical properties of the ITO film at room temperature is needed. To solve these limitations we develop the Magnetic Field Shielded Sputtering (MFSS) system. The MFSS is based on DMS and it has the plasma limiter, which compose the permanent magnet array (Fig.1). During the ITO thin film deposition in the MFSS process, the electrons in the plasma are trapped by the magnetic field at the plasma limiters. The plasma limiter, which has a negative potential in the MFSS process, prevents to the damage by negative oxygen ions bombardment, and increases the heat(-) up effect by the Ar ions in the bulk plasma. Fig. 2. shows the electrical properties of the MFSS ITO thin film and DMS ITO thin film at room temperature. With the increase of the sputtering pressure, the resistivity of DMS ITO increases. On the other hand, the resistivity of the MFSS ITO slightly increases and becomes lower than that of the DMS ITO at all sputtering pressures. The lowest resistivity of the DMS ITO is $1.0{\times}10-3{\Omega}{\cdot}cm$ and that of the MFSS ITO is $4.5{\times}10-4{\Omega}{\cdot}cm$. This resistivity difference is caused by the carrier mobility. The carrier mobility of the MFSS ITO is 40 $cm^2/V{\cdot}s$, which is significantly higher than that of the DMS ITO (10 $cm^2/V{\cdot}s$). The low resistivity and high carrier mobility of the MFSS ITO are due to the magnetic field shielded effect. In addition, although not shown in this paper, the roughness of the MFSS ITO thin film is lower than that of the DMS ITO thin film, and TEM, XRD and XPS analysis of the MFSS ITO show the nano-crystalline structure. As a result, the MFSS process can effectively prevent to the high energy negative oxygen ions bombardment and supply activation energies by accelerating Ar ions in the plasma; therefore, high quality ITO can be deposited at room temperature.

• Journal of Information Display
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• v.13 no.2
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.453-456
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• 1998

The electrical properties of $Si_{1-x}Ge_{x}$ samples have been investigated. The sample structures were grown by MBE (molecular geam epitaxy) with Ge mole-fraction of x=0.0, x=0.05, x=0.1, and x=0.2. To examine the influence of the thermal processing, the $O_{2}$ and N$_{2}$ process were performed at 800[.deg. C] and 900[.deg. C], respectively. After this thermal process, hall measurements have been done over a wide range of the ambient temperature between 320[.deg. K] and 10[.deg. K] to find the temperature dependence using the comparessed-He gas system. The Ge-rich layer has been formed at the $SiO_{2}$/SiGe interface and it has an effect on the hall mobility. And it has been found that hall mobility was increased by the $N_{2}$ annealing process comparing with dry oxidation process at both 800[.deg.C] and900[.deg. C].