• Journal of Korean Society of Industrial and Systems Engineering
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• v.45 no.4
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• pp.233-239
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• 2022

The injection molding process is a process in which thermoplastic resin is heated and made into a fluid state, injected under pressure into the cavity of a mold, and then cooled in the mold to produce a product identical to the shape of the cavity of the mold. It is a process that enables mass production and complex shapes, and various factors such as resin temperature, mold temperature, injection speed, and pressure affect product quality. In the data collected at the manufacturing site, there is a lot of data related to good products, but there is little data related to defective products, resulting in serious data imbalance. In order to efficiently solve this data imbalance, undersampling, oversampling, and composite sampling are usally applied. In this study, oversampling techniques such as random oversampling (ROS), minority class oversampling (SMOTE), ADASYN(Adaptive Synthetic Sampling), etc., which amplify data of the minority class by the majority class, and complex sampling using both undersampling and oversampling, are applied. For composite sampling, SMOTE+ENN and SMOTE+Tomek were used. Artificial neural network techniques is used to predict product quality. Especially, MLP and RNN are applied as artificial neural network techniques, and optimization of various parameters for MLP and RNN is required. In this study, we proposed an SA technique that optimizes the choice of the sampling method, the ratio of minority classes for sampling method, the batch size and the number of hidden layer units for parameters of MLP and RNN. The existing sampling methods and the proposed SA method were compared using accuracy, precision, recall, and F1 Score to prove the superiority of the proposed method.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.5
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• pp.254-259
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• 2003

In the fabrication process of transparent conducting thin films of the ATO (antimony-doped tin oxide) on a soda lime glass substrate by a sol-gel dip coating method, the effects of the $SiO_2$ buffer layer formed on the substrate and $N_2$ annealing treatment were investigated by XPS (X-ray photoelectron spectroscopy) analysis. Optical transmittance and electrical resistivity of the 400 nm-thick ATO thin films which were deposited on $SiO_2$ buffer layer/soda lime glass and then annealed under nitrogen atmosphere were 84 % and $5.0\times 10^{-3}\Omega \textrm{cm}$ respectively. The XPS analysis confirmed that a $SiO_2$ buffer layer inhibited Na ion diffusion from the substrate, resulting in prohibiting the formation of a secondary phase such as $Na_2SnO_3$ and SnO and increasing Sb ion concentration and ratio of $Sb^{5+}/Sb^{3+}$ in the film. And it was also found that $N_2$ annealing treatment leads to the reduction of $Sn^{4+}$as well as $Sb^{5+}$ however the reduction of $Sn^{4+}$ is more effective and therefore consequently results in decrease in the electrical resistivity to produce an excellent electrical properties of the film.

• Korean Journal of Materials Research
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• v.22 no.1
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• pp.24-28
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• 2012

$In_2O_3$ films were deposited by RF magnetron sputtering on a glass substrate and then the effect of post deposition annealing in nitrogen atmosphere on the structural, optical and electrical properties of the films was investigated. After deposition, the annealing process was conducted for 30 minutes at 200 and $400^{\circ}C$. XRD pattern analysis showed that the as deposited films were amorphous. When the annealing temperature reached 200-$400^{\circ}C$, the intensities of the $In_2O_3$ (222) major peak increased and the full width at half maximum (FWHM) of the $In_2O_3$ (222) peak decreased due to the crystallization. The films annealed at $400^{\circ}C$ showed a grain size of 28 nm, which was larger than that of the as deposited amorphous films. The optical transmittance in the visible wavelength region also increased, while the electrical sheet resistance decreased. In this study, the films annealed at $400^{\circ}C$ showed the highest optical transmittance of 76% and also showed the lowest sheet resistance of $89{\Omega}/\Box$. The figure of merit reached a maximum of $7.2{\times}10^{-4}{\Omega}^{-1}$ for the films annealed at $400^{\circ}C$. The effect of the annealing on the work-function of $In_2O_3$ films was considered. The work-function obtained from annealed films at $400^{\circ}C$ was 7.0eV. Thus, the annealed $In_2O_3$ films are an alternative to ITO films for use as transparent anodes in OLEDs.

• Journal of Sensor Science and Technology
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• v.5 no.3
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• pp.101-108
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• 1996

The silicon $p^{+}-n$ junction diodes were fabricated. The fabricated wafers were treated by single or double annealing steps. Single annealing process was performed by diffusion of either Au or Pt into the wafer under the oxygen or nitrogen ambient at $800{\sim}1010^{\circ}C$. Second annealing step involved additional annealing of the single annealed wafer under the oxygen ambient at $800{\sim}1010^{\circ}C$ for one hour. Electrical characteristics of the diodes were investigated to evaluate the effect of the annealing treatments. In the case of single annealing under nitrogen ambient at $1010^{\circ}C$ for one hour, the amount of leakage current of Pt diffused diode was 75 times larger than that of Au diffused one. The optimum processing condition to achieve high speed silicon $p^{+}-n$ junction diodes from this study was obtained when Pt diffused wafer(treated under the nitrogen ambient at $1010^{\circ}C$ for one hour) was secondly annealed in an oxygen ambient at $800^{\circ}C$ for one hour. The resulting leakage current of two step annealed diodes were remarkably reduced to 1/1100 of the single annealed one. The diode characteristics such as recovery time, breakdown voltage, leakage current, and forward voltage were 4ns, 138V, 1.72nA, and 1V, respectively.

• Transactions of Materials Processing
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• v.7 no.5
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• pp.439-444
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• 1998

Recently many automotive parts have been made with stainless steels by deep drawing processes, But there are various problems occurred in deep drawing works of stainless steels compared with low carbon steels. For the severe deep drawing of complex cylindrical housing optimum process planning is required to eliminate intermediate annealing improve shape accuracy and maintain surface integrity without drawing defects such as tears wrinkles and scratches or galling. Therefore in this study a sample process planning of the severe of the severe deep drawing process is applied to a complex cylindrical housing needed for a 6 multi-stepped deep drawing of type STS 305 . A series of experiments are performed to investigate optimum process variables such as drawing rate radius and clearance. Through experiments the variations of the thickness strain distribution and hardness distribution in each drawing step are observed. Also the effects of other factors on formability such as drawing oil, blank holding force and die geometry are examined and discussed.

• Korean Journal of Materials Research
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• v.13 no.1
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• pp.24-30
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• 2003

The Raney Ni catalyst was fabricated by mechanochemically process(MC process) in the Al-Ni system. Intermetallic compound obtained by mechanical alloying was leached in an alkaline solution. The characteristics of the mechanically alloyed powder and Raney Ni catalyst were analyzed by XRD, ICP-AES and EXAFS. In Al-50wt.%Ni, the metastable intermetallic compound phase close to AlNi phase was obtained by mechanical alloying unlike Al-Ni equilibrium phase diagram. The metastable intermetallic compound was transformed into $Al_3$$Ni_2$phase via the annealing at $750^{\circ}C$. The microstructure of Raney Ni fabricated by MC process was mainly bcc Ni including fcc Ni.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.5
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• pp.357-360
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• 2019

We demonstrate an alignment technology using an imprinting process on an inorganic NiOx film. The aligned nanopattern was fabricated on a silicon wafer by laser interference lithography. The aligned nano pattern was then imprinted onto the sol-gel driven NiOx film using an imprinting process at an annealing temperature of $150^{\circ}C$. After the imprinting process, parallel grooves had been formed on the NiOx film. Atomic force microscopy and water contact angle measurements were performed to confirm the parallel groove on the NiOx film. The grooves caused liquid crystal alignment through geometric restriction, similar to grooves formed by the rubbing process on polyimide. The liquid crystal cell exhibited a pretilt angle of $0.2^{\circ}$, which demonstrated homogeneous alignment.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.406-406
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• 2016

To get high efficiency n-type crystalline silicon solar cells, passivation is one of the key factor. Tunnel oxide (SiO2) reduce surface recombination as a passivation layer and it does not constrict the majority carrier flow. In this work, the passivation quality enhanced by different chemical solution such as HNO3, H2SO4:H2O2 and DI-water to make thin tunnel oxide layer on n-type crystalline silicon wafer and changes of characteristics by subsequent annealing process and firing process after phosphorus doped amorphous silicon (a-Si:H) deposition. The tunneling of carrier through oxide layer is checked through I-V measurement when the voltage is from -1 V to 1 V and interface state density also be calculated about $1{\times}1012cm-2eV-1$ using MIS (Metal-Insulator-Semiconductor) structure . Tunnel oxide produced by 68 wt% HNO3 for 5 min on $100^{\circ}C$, H2SO4:H2O2 for 5 min on $100^{\circ}C$ and DI-water for 60 min on $95^{\circ}C$. The oxide layer is measured thickness about 1.4~2.2 nm by spectral ellipsometry (SE) and properties as passivation layer by QSSPC (Quasi-Steady-state Photo Conductance). Tunnel oxide layer is capped with phosphorus doped amorphous silicon on both sides and additional annealing process improve lifetime from $3.25{\mu}s$ to $397{\mu}s$ and implied Voc from 544 mV to 690 mV after P-doped a-Si deposition, respectively. It will be expected that amorphous silicon is changed to poly silicon phase. Furthermore, lifetime and implied Voc were recovered by forming gas annealing (FGA) after firing process from $192{\mu}s$ to $786{\mu}s$. It is shown that the tunnel oxide layer is thermally stable.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.348-348
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• 2011

Carbon nanotube (CNT) field effect transistors and sensors use CNT as a current channel, of which the resistance varies with the gate voltage or upon molecule adsorption. Since the performance of CNT devices depends very much on the CNT/metal contact resistance, the CNT/electrode contact must be stable and the contact resistance must be small. Depending on the geometry of CNT/electrode contact, it can be categorized into the end-contact, embedded-contact (top-contact), and side-contact (bottom-contact). Because of difficulties in the sample preparation, the end-contact CNT device is seldom practiced. The embedded-contact in which CNT is embedded inside the electrode is desirable due to its rigidness and the low contact resistance. Fabrication of this structure is complicated, however, because each CNT has to be located under a high-resolution microscope and then the electrode is patterned by electron beam lithography. The side-contact is done by depositing CNT electrophoretically or by precipitating on the patterned electrode. Although this contact is fragile and the contact resistance is relatively high, the side-contact by far has been widely practiced because of its simple fabrication process. Here we introduce a simple method to embed CNT inside the electrode while taking advantage of the bottom-contact process. The idea is to utilize a eutectic material as an electrode, which melts at low temperature so that CNT is not damaged while annealing to melt the electrode to embed CNT. The lowering of CNT/Au contact resistance upon annealing at mild temperature has been reported, but the electrode in these studies did not melt and CNT laid on the surface of electrode even after annealing. In our experiment, we used a eutectic Au/Al film that melts at 250$^{\circ}C$. After depositing CNT on the electrode made of an Au/Al thin film, we annealed the sample at 250$^{\circ}C$ in air to induce eutectic melting. As a result, Au-Al alloy grains formed, under which the CNT was embedded to produce a rigid and low resistance contact. The embedded CNT contact was as strong as to tolerate the ultrasonic agitation for 90 s and the current-voltage measurement indicated that the contact resistance was lowered by a factor of 4. By performing standard fabrication process on this CNT-deposited substrate to add another pair of electrodes bridged by CNT in perpendicular direction, we could fabricate a CNT cross junction. Finally, we could conclude that the eutectic alloy electrode is valid for CNT sensors by examine the detection of Au ion which is spontaneously reduced to CNT surface. The device sustatined strong washing process and maintained its detection ability.

• Journal of the Korean Vacuum Society
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• v.14 no.2
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• pp.91-96
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• 2005

The silicon-on-insulator (SOI) wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by SRIM simulation that 65keV proton implantation is required for a SOI wafer (200nm SOI, 400nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the $6\~9\times10^{16}\;H^+/cm^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. Direct wafer bonding is performed by joining two wafers together after creating hydrophilic surfaces by a modified RCA cleaning, and IR inspection is followed to ensure a void free bonding. The wafer splitting was accomplished by annealing at the predetermined optimum condition, and high temperature annealing was then performed at $1,100^{\circ}C$ for 60 minutes to stabilize the bonding interface. TEM observation revealed no detectable defect at the SOI structure, and the interface trap charge density at the upper interface of the BOX was measured to be low enough to keep 'thermal' quality.