• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.853-858
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• 2003

In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.

• Transactions of Materials Processing
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• v.13 no.2
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• pp.137-141
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• 2004

The large deformation at cryogenic temperature is expected as one of the effective methods to produce large bulk ultrafine grained materials. The effects of annealing temperature, 150∼$300^{\circ}C$, on microstructures and mechanical properties of the sheets received 85% reduction at cryogenic temperature were investigated, in comparison with those at room temperature. Annealing of 5083 Al alloy deformed 85%, at $200^{\circ}C$ for an hour,. resulted in the considerable increase of tensile elongation without the great loss of strength and the occurrence of equiaxed grains less than 300nm in diameter.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.69-72
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level syntehsis consist of compiling, partitioning, scheduling This paper we study the partitioning process, and analysis the min-cut algorithm and simulated annealing algorithm.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.85-87
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• 2003

Intermediate annealing was carried out during wire drawing for uniform deformation of 500 m class Bi-2223/Ag HTS tapes. Wire drawing force was measured to evaluate the uniformity of wire deformation along the length. To prevent sausage and filament breakage of wire, drawing stress was controlled below 200 MPa by using intermediate annealing process. Thickness and width of the rolled tapes was measured 0.23 mm and 4.1 mm with low deviation $\pm$ 0.08 mm and $\pm$ 0.09 mm, respectively. The critical current of the 500 m tapes was measured 33.7 A $\pm$ 3.7 A by continuous critical current measurement system.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.307-309
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• 2005

We investigated light absorption layer effect on metal-induced lateral crystallization (MILC) growth rate and MILC thin films transistors (TFTs). As annealing method, we used scanning-rapid thermal annealing (RTA). MILC growth rate which was crystallized by light absorption layer and using scanning-RTA was 3 times than normal MILC which was without light absorption layer growth rate. Also we compared MILC TFTs characteristics which were combined to light absorption layer with conventional MILC TFTs. After scanning-RTA process, MILC-TFTs which were with light absorption layer were superior to conventional MILC-TFTs. With this new MILC-TFTs structure, we could reduced crystallization time and obtain good electrical properties.

• Computational Structural Engineering
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• v.5 no.2
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• pp.93-104
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• 1992

The final objective of optimization methods is to find global optimum accurately and efficiently. The optmization processes by simulated annealing and genetic algorithm which have stochastic search process are examined and are applied to several mathematical models and truss, beam structures. Then the robustnesses of these two methods are studied and compared with the results of deterministic optimization methods from the viewpoints of reliability and running time in obtaining the global optimum.

• Journal of Surface Science and Engineering
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• v.40 no.5
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• pp.214-218
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• 2007

The objective of this study is to evaluate the diffusion behavior of Al and Si from a coatings in the microstucture of Fe-Si steel. Steel samples deposited with Al-Si alloy are prepared by ion plating process, followed by annealing treatments for diffusion at $1050^{\circ}C$. Several intermetallic phases are found in the coatings and they are identified as Fe-Al and an orderd Fe-Si compounds. Series of different concentration profiles through the sample have been obtained and Si content reaches about 5 wt% in case of 90 minutes of diffusion time.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.1-6
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• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.396-399
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• 2009

Thin-film transistors (TFTs) with an aluminum indium oxide (AIO) channel layer were fabricated via a simple and low-cost sol-gel process. Effects of annealing temperature and time were investigated for better TFT performance. The sol-gel AIO TFTs were annealed as low as $350^{\circ}C$. They exhibit n-type semiconductor behavior, a mobility higher than 19 $cm^2/V{\cdot}s$ and an onto-off current ratio greater than $10^8$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.4
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• pp.595-599
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• 1996

The behaviour of the internal bubbles present in $CaF_{2}$ crystals was characterized crystallographically using a variety of the mircroscopical technique. The bubble defects were found to be aligned on the characteristic planes and directions depending on the crystals structure of the $CaF_{2}$. The AFM analysis revealed that these behaviors are related to the S-surface formation by the negative grain growth mechanism.