• Journal of the Korean Society for Precision Engineering
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• v.21 no.5
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• pp.24-31
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• 2004

Masking effect of the nanoscratched silicon (100) surface was studied and applied to a maskless nanofabrication technique. First, the surface of the silicon (100) was machined by ductile-regime nanomachining process using the scratch option of the Nanoindenter${ \circledR}$ XP. To clarify the possibility of the nanoscratched silicon surfaces for the application to wet etching mask, the etching characteristic with a KOH solution was evaluated at room temperature. After the etching process, the convex nanostructures were made due to the masking effect of the mechanically affected layer. Moreover, the height and the width of convex structures were controlled with varying normal loads during nanoscratch.

• Journal of Sensor Science and Technology
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• v.8 no.4
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• pp.308-313
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• 1999

This paper will present an anisotropic etching in TMAH technique used in the fabrication of three-dimensional magnetic field vector sensor based on angled Hall plate structure. This sensor design relies on simultaneously detecting all magnetic field vector components using Hall plates that are imbedded into the silicon [111] sloped-surface of bulk micromachined cavity by the anisotropic etching of [100] silicon. The fabricated Hall elements has relatively improved sensitivity compare to convensional Hall elements for three-dimensional magnetic field sensing. The product sensitivity of 547V/AT at the supply current of 1.0mA was achived. The corresponding limit in the detection of magnrtic field is 0.07G that calculated by measured power spectral density(PSD) in magnetic sensor output.

• New & Renewable Energy
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• v.2 no.2 s.6
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• pp.4-8
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient Reff lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• 한국신재생에너지학회:학술대회논문집
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• 2007.06a
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• pp.295-298
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• 2007

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating(ARC) and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si ARC layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layers were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The structure of porous Si layers was investigated with SEM. The formation of a nanoporous Si layer about 100nm thick on the textured silicon wafer result in a reflectance lower than 5% in the wavelength region from 500 to 900nm. Such a surface modification allows improving the Si solar cell characteristics. An efficiency of 13.4% is achieved on a monocrystalline silicon solar cell using the electrochemical technique.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.183-186
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient $R_{eff}$ lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.26-31
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• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1522-1526
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• 2005

In this study, the fabrication of large area silicon mirror is accomplished by anisotropic etching using MEMS for implementation of integrated optical pickup and the process condition is also established for improving the mirror surface roughness. Until now, few results have been reported about the production of highly stepped $9.74^{\circ}$ off-axis-cut silicon wafer using wet etching. In addition rough surface of the mirror is achieved in case of long etching time. Hence a novel method called magnetorheolocal finishing is introduced to enhancing the surface quality of the mirror plane. Finally, areal peak to valley surface roughness of mirror plane is reduced about 100nm in large area of $mm^2$ and it is applicable to optical pickup using infrared wavelength.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.741-744
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.739-742
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• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

• Journal of the Korean Ceramic Society
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• v.46 no.6
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• pp.685-688
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• 2009

Surface Texturing is very important process for high cell efficiency in crystalline silicon solar cell. Anisotropic texturing with an alkali etchant was known not to be able to produce uniform surface morphology in multi-crystalline silicon (mc-Si), because of its different etching rate with random crystal orientation. In order to reduce surface reflectance of mc-Si wafer, the general etching tendency was studied with HF/HN$O_3$/De-ionized Water acidic solution. And the surface structures of textured mc-Si in various HF/HN$O_3$ ratios were compared. The surface morphology and reflectance of textured silicon wafers were measured by FE-SEM and UVvisible spectrophotometer, respectively. We obtained average reflectance of $16{\sim}19$% for wavelength between 400 nm and 900 nm depending on different etching conditions.