• ETRI Journal
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• v.32 no.2
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• pp.214-221
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• 2010

Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.230-238
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• 2005

An orthogonal frequency division multiplexing (OFDM) system consists of a number of independently modulated subcarriers and, thus, a high peak-to-average power ratio (PAR) can occur when the subcarriers are added coherently. The high PAR brings such disadvantages as an increased complexity of the analog-to-digital (ADC) and digital-to-analog (DAC) converters and a reduced efficiency of the radio frequency (RF) power amplifier. In this paper, we propose a novel PAR reduction scheme called selective mapping of partial tones (SMOPT). The SMOPT scheme has a reduced complexity, lower sensitivity to peak reduction tones (PRT) positions, and a shorter processing time as compared with the conventional tone reservation (TR) scheme. The performance of the SMOPT scheme is analyzed based on the IEEE 802.1la wireless local area network(WLAM) physical layer model. Numerical results show that the SMOPT scheme outperforms the TR scheme under various scenarios.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.25 no.2
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• pp.363-373
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• 1995

The aim of this study was to evaluate and compare observer performance between conventional radiographs and their digitized images for the detection of bone loss in the bifurcation of mandiblar first molar. One dried human mandible with minimal periodontal bone loss around the first molar was selected and serially enlarged 17 step defects were prepared in the bifurcation area. The mandible was radiographed with exposure time of 0.12, 0.20, 0.25, 0.32, 0.40, 0.64 seconds, after each successive step in the preperation and all radiographs were digitized with IBM-PC/32 bit-Dx compatible, video camera (VM-S8200, Hitachi Co., Japan), and color monitor(Multisync 3D, NEC, Japan). Sylvia Image Capture Board for the ADC(analog to digital converter) was used. The obtained results were as follows: 1. In the conventional radiographs, the mean score of the readability was higher at the condition of exposure time with 0.32 second. Also, as the size of artificial lesion was increased, the readability of radiographs was elevated (P<0.05). 2. In the digital images, the mean score of the readability was higher at the condition of exposure time with 0.40 second. Also, as the size of artificial lesion was increased, the readability of digital images was elevated(P<0.05). 3. At the same exposure time, the mean scores of readibility were mostly higher in the digitized images. As the exposure time was increased, the digital images were superior to radiographs in readability. 4. As the size of lesion was changed, the digital images were superior to radiographs in detecting small lesion. 5. The coefficient of variation of mean score has no significant difference between digital images and radiographs.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.256-261
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• 2011

In this paper, a design and an implementation of an Analog to Digital (A/D) converter are introduced for the conversion of monitored battery cell voltage in the cell voltage monitoring(CVM) system in battery management system(BMS), which is one of the key devices of ECO hybrid cars. The A/D converter in CVM system required a middle conversion speed and a high resolution, therefore, a successive approximate register(SAR) typed A/D converter with 10 bits resolution has been designed and implemented using Magna 0.6um 40V process. The measurement result which kept ${\pm}1$ LSB accuracy in the full scale range(FSR) of 5V, showed the usefulness of the SAR typed A/D converter in realizing a CVM system.

• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.24 no.1
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• pp.85-94
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• 1994

The purposes of this study were clinical comparison and evaluation between digital radiography and conventional radiography for the detection of artificial interproximal caries. Four freshly extracted, unrestored posterior teeth were obtained and caries was simulated by drilling semicircled defects with variable size at the interproximal surface of each tooth. The experiments were performed with IBM-PC/32 bit-DX compatible, video camera(VM-S8200, Hitachi Co., Japan), and color monitor(Multisync 3D, NEC, Japan). Sylvia Image Capture Board for the ADC(analog to digital converter) was used, and spatial resolution was 512 × 480 with 256 gray levels. The obtained results were as follows: 1. At the condition of under exposure, the radiographs were superior to the digital images in readability. Also, as the size of the artificial lesion was increased, readability of the radiographs was elevated. 2. The digital images were superior to the radiographs in readability especially under over exsposure. 3. As the exposure time and size of lesion was increased, the gray level of region of interest of the digital image was decreased proportionally. 4. As the F-value of average gray level of region of interest at individual exposure time and size of lesion, gray level of the all lesion sizes was decreased in comparison with that of the normal enamel.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.612-616
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• 2016

Gamma-ray must be detected and processed immedietely after generation of it in the circumstances where it exists. Software methology may be used to process randomly generated signals, but its memory size and processing time become large. By the way, the hardware circuit to detect randomly generated signals is generalized in industrial site, while those circuits are not able to answer to the cases whose amplitude are very small and also speed high. We researched and developed hardware based peak-hold circuit that is able to detect peaks of gamma-ray signals through direct reading out their values by ADC at the time of maximum reaching for the small amplitude and high speed signals, and proposed and estimated its results in this paper. This peak-hold circuit is adequate to use in the radiation circumstances in which the gamma-rays are heavy because its circuit can catch high speed signals efficiently without software signal processing supports.

• Journal of Radiation Protection and Research
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• v.41 no.2
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• pp.81-86
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• 2016

Background: For positron emission tomography (PET) application, cadmium zinc telluride (CZT) has been investigated by several institutes to replace detectors from a conventional system using photomultipliers or Silicon-photomultipliers (SiPMs). The spatial and energy resolution in using CZT can be superior to current scintillator-based state-of-the-art PET detectors. CZT has been under development for several years at the Korea Atomic Energy Research Institute (KAERI) to provide a high performance gamma ray detection, which needs a single crystallinity, a good uniformity, a high stopping power, and a wide band gap. Materials and Methods: Before applying our own grown CZT detectors in the prototype PET system, we investigated preliminary research with a developed discrete type data acquisition (DAQ) system for coincident events at 128 anode pixels and two common cathodes of two CZT detectors from Redlen. Each detector has a $19.4{\times}19.4{\times}6mm^3$ volume size with a 2.2 mm anode pixel pitch. Discrete amplifiers consist of a preamplifier with a gain of $8mV{\cdot}fC^{-1}$ and noise of 55 equivalent noise charge (ENC), a $CR-RC^4$ shaping amplifier with a $5{\mu}s$ peak time, and an analog-to-digital converter (ADC) driver. The DAQ system has 65 mega-sample per second flash ADC, a self and external trigger, and a USB 3.0 interface. Results and Discussion: Characteristics such as the current-to-voltage curve, energy resolution, and electron mobility life-time products for CZT detectors are investigated. In addition, preliminary results of gamma ray imaging using 511 keV of a $^{22}Na$ gamma ray source were obtained. Conclusion: In this study, the DAQ system with a CZT radiation sensor was successfully developed and a PET image was acquired by two sets of the developed DAQ system.