• Title/Summary/Keyword: Analog-Digital Conversion

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A Distortionless Digital PWM Implementation by means of a Non-integer delay FIR filtering (소수형 디지털연산 알고리즘을 이용한 디지털 PWM의 고유한 비선형특성의 보상)

  • 정진훈;정동호
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.2427-2430
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    • 2003
  • A uniformly sampled digital pulse-width modulation adopting a pre-compensation filter scheme for applications in high-resolution digital-to-analog data conversion is described. It is shown that linearization of the intrinsic distortion resulting in uniformly sampled pulse-width modulation can be achieved by using a non-integer delay digital filter embedded within a noise shaping re-quantizer.

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Linear Unequal Error Protection Codes based on Terminated Convolutional Codes

  • Bredtmann, Oliver;Czylwik, Andreas
    • Journal of Communications and Networks
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    • v.17 no.1
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    • pp.12-20
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    • 2015
  • Convolutional codes which are terminated by direct truncation (DT) and zero tail termination provide unequal error protection. When DT terminated convolutional codes are used to encode short messages, they have interesting error protection properties. Such codes match the significance of the output bits of common quantizers and therefore lead to a low mean square error (MSE) when they are used to encode quantizer outputs which are transmitted via a noisy digital communication system. A code construction method that allows adapting the code to the channel is introduced, which is based on time-varying convolutional codes. We can show by simulations that DT terminated convolutional codes lead to a lower MSE than standard block codes for all channel conditions. Furthermore, we develop an MSE approximation which is based on an upper bound on the error probability per information bit. By means of this MSE approximation, we compare the convolutional codes to linear unequal error protection code construction methods from the literature for code dimensions which are relevant in analog to digital conversion systems. In numerous situations, the DT terminated convolutional codes have the lowest MSE among all codes.

System Strategies for Time-Domain Emission Measurements above 1 GHz

  • Hoffmann, Christian;Slim, Hassan Hani;Russer, Peter
    • Journal of electromagnetic engineering and science
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    • v.11 no.4
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    • pp.304-310
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    • 2011
  • The application of time-domain methods in emission measurement instruments allows for a reduction in scan time by several orders of magnitude and for new evaluation methods to be realized such as the real-time spectrogram to characterize transient emissions. In this paper two novel systems for time-domain EMI measurements above 1 GHz are presented. The first system combines ultra-fast analog-to-digital-conversion and real-time digital signal processing on a field-programmable-gate-array (FPGA) with ultra-broadband multi-stage down-conversion to enable measurements in the range from 10 Hz to 26 GHz with high sensitivity and full-compliance with the requirements of CISPR 16-1-1. The required IF bandwidths were added to allow for measurements according to MIL-461F and DO-160F. The second system realizes a system of time-interleaved analog-to-digital converters (ADCs) and has an upper bandwidth limit of 4 GHz. With the implementation of an automatic mismatch calibration, the system fulfills CISPR 16-1-1 dynamic range requirements. Measurements of the radiated emissions of electronic consumer devices and household appliances like the non-stationary emissions of a microwave oven are presented. A measurement of a personal computer's conducted emissions on a power supply line according to DO-160F is given.

A Design of CMOS Analog-Digital Converter for High-Speed . Low-power Applications (고속 . 저전력 CMOS 아날로그-디지탈 변환기 설계)

  • Lee, Seong-Dae;Hong, Guk-Tae;Jeong, Gang-Min
    • The Transactions of the Korea Information Processing Society
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    • v.2 no.1
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    • pp.66-74
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    • 1995
  • A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at +5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

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A CMOS Image Sensor with Analog Gamma Correction using a Nonlinear Single Slope ADC (비선형 단일 기울기 ADC를 사용하여 아날로그 감마 보정을 적용한 CMOS 이미지 센서)

  • Ham Seog-Heon;Han Gunhee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.65-70
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    • 2006
  • An image sensor has limited dynamic range while the human eye has logarithmic response over wide range of light intensity. Although the sensor gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye response. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This Paper proposes a CMOS image sensor (CIS) with a nonlinear analog-to-digital converter (AU) which performs analog gamma correction. The CIS with the proposed nonlinear analog-to-digital conversion scheme was fabricated with a $0.35{\mu}m$ CMOS process. The analog gamma correction using the proposed nonlinear ADC CIS provides the 2.2dB peak-signal-to-noise-ratio(PSM) improved image qualify than conventional digital gamma correction. The PSNR of the image obtain from the digital gamma correction is 25.6dB while it is 27.8dB for analog gamma correction. The PSNR improvement over digital gamma correction is about $28.8\%$.

A Study on the Impact of Cable TV 8VSB Conversion on Subscriber Retention and Consumer Welfare (케이블TV 8VSB 전환이 가입자 유지 및 소비자 후생에 미치는 영향에 관한 연구)

  • Kim, Jee-Hoon;Lee, Yeong-Ju
    • Journal of Broadcast Engineering
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    • v.23 no.6
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    • pp.824-835
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    • 2018
  • In this study, the impact on the number of cable TV subscribers as well as the profit of cable TV has been examined, and the impact on enlarging the digital broadcast viewing rights of cable TV subscribers and viewers' welfare has also been examined. We investigated the trends in the number of analog and 8VSB subscribers and revenue of cable TV operators by region and analyzed based on changes in the number of channels provided by each operator. The results show that analog subscribers and digital subscribers are delaying their departure through 8VSB conversion, and VOD subscription fees and home shopping transmission fees have a significant impact on operating profit. Subscribers, as they switched over to 8VSB, have become able to view channels of various genres with clear picture quality for a same subscription fee, and the program providers could offer programs to more customers. The government's deregulation policy due to the changes in broadcasting environment led to the facilitation of digital conversion of Pay-TV and improvement of viewers' welfare.

A Study on Design and Implementation of Digital Filter (디지탈 필터의 설계 및 구현에 관한 연구)

  • Seo, Eun-Taek;Chung, C.H.
    • Proceedings of the KIEE Conference
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    • 1993.07a
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    • pp.447-449
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    • 1993
  • Digital filter is a signal processor which converts the sequence input sampled from analog signal into another sequence output. It includes software routines which filter digital signal, a computer system for executing the routines, and a data acquisition system which implements A/D, D/A signal conversion. In this paper, a data acquisition system is designed and implemented for one-board computer of MC68000. Also, the theory regarding signal conversion and and its problems occured in implementation are considered. And then, with the hardware implemented like this, design of a digital low-pass filter with the cutoff frequency of 200Hz is implemented, and related characteristics are considered.

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A 6bit 800MSample/s A/D Converter Design for Hard Disk Drive Read Channel (하드디스크 드라이브 읽기 채널용 6bit 800MSample/s 아날로그/디지털 변환기의 설계)

  • 정대영;장흥석;신경민;정강민
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.164-167
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    • 2000
  • This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

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Digitization Impact on the Spaceborne Synthetic Aperture Radar Digital Receiver Analysis (위성탑재 영상레이다 디지털 수신기에서의 양자화 영향성 분석)

  • Lim, Sungjae;Lee, Hyonik;Sung, Jinbong;Kim, Seyoung
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.49 no.11
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    • pp.933-940
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    • 2021
  • The space-borne SAR(Synthetic Aperture Radar) system radiates the microwave signal and receives the backscattered signal. The received signal is converted to digital at the Digital Receiver, which is implemented at the end of the SAR sensor receiving chain. The converted signal is formated after signal processing such as filtering and data compression. Two quantization are conducted in the Digital Receiver. One quantization is an analog to digital conversion at ADC(Analog-Digital Converter). Another quantization is the BAQ(Block Adaptive Quantization) for data compression. The quantization process is a conversion from a continuous or higher bit precision to a discrete or lower bit precision. As a result, a quantization noise is inevitably occurred. In this paper, the impact of two quantization processes are analyzed in a view of SNR degradation.

Characteristics of Analog Encoder for SRM Drive

  • Park, Sung-Jun;Ahn, Jin-Woo
    • KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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    • v.12B no.1
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    • pp.31-36
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    • 2002
  • In a switched reluctance motor drive, it is important to synchronize the stator phase excitation with the rotor position; therefore, the position of rotor is an essential information. Although optical encoders or resolvers are used to provide the position information, these sensors are expensive. Moreover, in the high-speed region, switching angles are fluctuated back and forth out of the preset value, which is caused by the sampling period of the microprocessor. In this paper, a low cost analog encoder suitable for practical applications is proposed. And the control algorithm to generate switching signals using a simple digital logic is presented. The validity of the proposed analog encoder with a proper logic controller is verified from the experiments.