• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.34-45
• /
• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.3
• /
• pp.184-196
• /
• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• The Journal of the Convergence on Culture Technology
• /
• v.6 no.3
• /
• pp.427-430
• /
• 2020

The multi-channel analog signal to digital signal conversion is increasing in the field of IoT and medical measurement equipments. It has chip area and power consumption constraints to use a few single or 2_channel ADC for multi_channel application. This paper described to design and implement a proposed comb filter for multi-channel, 24bit ADC. The function of proposed comb filter is verified by matlab simulation and the FPGA test board. It was fabricated using SK Hynix 0.35㎛ CMOS standard process. The performance and chip size is compared with the existing design method that uses integrator/differentiator and FIR construction. The proposed comb filter is expected to use the IoT product and medical measurement equipments that require multi-channel, low power consumption and small hardware size.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.33 no.8
• /
• pp.65-74
• /
• 2005

It is required for getting the ring laser gyro output purely related to the input rotation to eliminate the output of the modulated angular vibration from the ring laser signal. In this paper we discuss the dither stripping methods of compensating the ring laser signal by converting the rate signal of dither detector from voltage to frequency for a dither type ring laser gyro. We discuss the differential methods for getting rid of the offset of the V-F signal. And we develope the methods of compensating the phase differences between the ring laser signals and the V-F differential signals by using analog integrator and digital time delays. And also, we develope the gain calculation method by comparing the standard deviations of the ring laser signals with V-F differential signals. We implemented these methods and analyzed the effectiveness of these methods by comparing the dither trapping methods.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.3
• /
• pp.455-464
• /
• 2019

The sensorless control based on the flux linkage of PM synchronous motors has excellent position estimation characteristics at low speeds. However, a limitation arises because the integrator of flux estimator is saturated by the DC offset generated during the analog to digital conversion(ADC) process of the measured current. In order to overcome this limitation, HPF with a low cutoff frequency is used. However, the estimation performance is deteriorated (Ed- the verb deteriorate already includes the meaning of 'problem') at high speed due to the low cutoff frequency, and increasing the cutoff frequency of the HPF induces further problems of phase leading and initial starting failure at low speeds. In this paper, the cutoff frequency of HPF was synchronized to the operation frequency of the motor: at low speeds the cutoff frequency was set to low in order to reduce the phase leading of the estimated flux, and at high speeds it was set to high to raise the DC offset removal performance. As a result, the operating range was increased by 200%. Furthermore, a phase compensation algorithm is proposed to reduce the phase leading of the HPF to less than 1.5 degrees over the full operating range. The proposed sensorless control algorithm was verified by experiment with a PM synchronous motor for a washing machine.