• Proceedings of the IEEK Conference
• /
• 2003.07c
• /
• pp.2677-2680
• /
• 2003

This paper describes the implementation of a 4 channel embedded DVR system. It receives analog video from CCD cameras and converts to 640${\times}$480 CCIR-656 digital video by 30 frames/sec. These digital images are compressed to the wevelet transformed image using hardware codec which is capable of 350:1 real-time compression and decompression. The DVR is working on linux and it implemented on an embedded system which is based on StrongARM processor. For the interface between processor system module and image processing module, GPIO and memory control module are used, device drivers are developed. Linux kernel source is customized. This paper provides techniques of embedded system development and embedded linux porting.

• Proceedings of the KIEE Conference
• /
• 1990.11a
• /
• pp.443-445
• /
• 1990

In this paper, a high speed graphic processor module with a real-time processing capability is proposed, where the module is design to be compatible to the standard VME bus and consists of TMS34010 Graphic processor, TMS44C251 frame buffer, 512KB system memory and BT101 digital to analog converter. The proposed graphic module is implemented and tested in real-time via experiments with an integrated system with other VME modules.

• Journal of the korean Society of Automotive Engineers
• /
• v.7 no.3
• /
• pp.64-73
• /
• 1985

In order to control ignition advance angle, this system is designed with Z-80 CPU, CTC (counter Timer Circuit), PIO(Parallel Input Output), A/D Converter and Memory, etc. Serial pulses from speed sensor and analog voltage from pressure sensor are converted to digital data. In order to reduce the error of ignition advance angle output, the reference of ignition advance angle output is set 56.25 before TDC(Top Dead Center). The table of ignition advance angle and program which have a main routine and subroutines are written into ROM ( 1 K-byte). The experimental result of this system is correspondent to the theoretical values of proposed ignition advance angle table. This system can be utilized to any other type of 4 cylinder vehicles for advance angle control by changing software.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1991.10a
• /
• pp.1-4
• /
• 1991

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• Proceedings of the KIEE Conference
• /
• 1999.11c
• /
• pp.693-696
• /
• 1999

This paper describes a new voltage recorder for the voltage management of a power distribution line by using a new voltage measurement technique. The RMS(Root Mean Square) voltage measurement for the power line under the assumption of a sinusoidal input voltage is taken by the full-wave rectifier, half-adder utilizing operational amplifier(OP) circuit. A/D converter utilizing a dual slope converter converts an analog voltage signal into a serial pulse. The pulse is counted with a single chip micro-controller, converted with the RMS voltage, and saved into a flash memory. In the last, a new voltage recorder with compact size and multifunction is developed. Also, Voltage Management System that can analyze the stored data via RS-232C cable is developed based on Windows 95 and Visual C++.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.10
• /
• pp.21-30
• /
• 1994

We discussed the Distributed Control System's design on preface and analyzed time of the real-time communication by using designed system. The DCS proposed in this thesis was implemented to network file system having recovery advantage and shared memory method to access file system of a Remote Station with ease. Also, this system minimized the network delay-time by using the real-time VME147 board. In implemented DCS, the performance analysis of real-time process of a Remote Station was done to get the total time for reak-tune communication from a Remote Station to the Central Station after terminating of process. For the analysis of system performance, we experiented by three steps. Firstly, we measuredthe processing the of LOOP function that real-time CPU convertes to-2,500~10.000 values from the input data of the Analog Interface Card. Secondly, we measured the processing time of the LOGIC function and the LOOP function. Lastly, we measured total processing time for communication from a Remote Station to the Centrol Station.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1141-1144
• /
• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• ETRI Journal
• /
• v.31 no.4
• /
• pp.393-398
• /
• 2009

The operation of a first-order 2-bit adaptive sigma-delta modulation system is described and discussed in this paper. The system operation is based on the combination of both "memory" and "look-ahead" estimation in the employed step-size adaptation algorithm of the basic quantizer. In comparison to simple systems and other adaptive sigma-delta systems, computer simulation results show that these features of the described system are responsible for the high SNR values and the extended dynamic range achieved for AC signals as well as the noise power reduction of almost 10 dB and the complete elimination of the idle tones for DC signals. However, such an advantageous performance requires the least possible multiplicative error accumulation, and this cannot be achieved without analog circuits of the highest possible accuracy.

• Journal of Institute of Control, Robotics and Systems
• /
• v.21 no.5
• /
• pp.477-481
• /
• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.6
• /
• pp.230-238
• /
• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.