• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.1
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• pp.47-53
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• 1999

CD-ROM(Compact Disk-Read Only Memory) is very attractive storage media because it has much storage space but is small size and portable. Optical pickup, one of the most important parts for reading data on a CD-ROM, is not produced tuned up. For the use of goods, we must tune up the optical pickup by adjusting the screw for adjustment. First, we developed analog servo system for optical pickup tuners. For eliminating some problems in analog servo system, this paper designed the modeling of digital servo system for optical pickup tuner. Though the characteristics of optical pickup are changed, the digital servo system for optical pickup tuner can easily apply to all pickup, and can reduce the measurement error among the optical pickup tuners. For the purpose of confirming the designed digital servo system, we produced data that specify the disk vibration and the disk eccentricity, and simulated servo system with MATLAB.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1962-1967
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• 2008

A event recorder system stores a train speed and the related information for train operation in real time. Using those information, we can analysis the train operation and the reason of train accident. Currently the event recorder only manipulate the data related the train operation mechanically and electrically. In this paper we propose the event recorder to record the voice communication between the manager in the control center and train operator. By recording the voice communication in the high speed train, the correctness of analysis of train accident can be increased. The system architecture of the event recorder with voice recording is studied and interface between other equipment is proposed. And the software architecture of new event recorder is developed. We study the method of converting analog voice signal into digital data and compressing method. Also the architecture of memory to store the compressed voice data and regeneration of original analog voice are studied.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.159-160
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• 2007

Two analog predsitorters (PDs) using the mixing operation are proposed to compensate for the memory effects of the power amplifier and then significantly cancel IM3 components with the independent control of IM3 terms. In the first PD, IM3 terms are generated by using mixing operation of low frequency terms. In the second PD, the double mixing operation of the fundamental components is used. For a two-tone signal with 20-MHz tone spacing, the notable IM3 suppression is achieved over a whole output power range.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.223-228
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• 2021

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.394-399
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• 1987

It is necessary for the speech samples to be stored in memory buffer before speech analyzers without a real time processor process them. In this paper, we propose an algorithm that uses the buffer efficiently, when the analog speech signal is converted to the digital samples by the analog to digital converter. In order to implement this method in real time, the buffer is divided into the starting buffer and the remaining buffer. Until a voiced speech is found, the converted samples are sequentially stored in the starting buffer, and then the buffer is shifted. When a voiced speech is found, the next samples are sequentally recorded in the remaining buffer.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.18-27
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• 2010

This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.2
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• pp.99-107
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• 2006

Magnetic nondestructive testing is very useful far detecting a crack on the surface or near of the surface of the ferromagnetic materials. The distribution of the magnetic flux leakage (DMFL) on a specimen has to be obtained quantitatively to evaluate the crack. The magnetic camera is proposed to obtain the DMFL at the large lift-off. The magnetic camera consists of a magnetic source, magnetic lens, analog to digital converters (ADCs), interface, and computer. The magnetic leakage fields or the distorted magnetic fields from the object, which are concentrated on the magnetic lens, are converted to analog electrical signals tv arrayed small magnetic sensors. These analog signals are converted to digital signals by the ADCs, and are stored, imaged, and processed by the interface and computer. However the magnetic camera has limitations with respect to converting and switching speed, full range and resolution, direct memory access (DMA), temporary storage speed and volume because common ADCs were used. Improved techniques, such as those that introduce the operational amplifier (OP-Amp), amplify the signal, reduce the connection line, and use the low pass filter (LPF) to increase the signal to noise ratio are necessary. This paper proposes the exclusive embedded ADC including OP-Amp, LPF, microprocessor and DMA circuit for the magnetic camera to satisfy the conditions mentioned above.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.41-49
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• 2010

Being popularized the use of portable entertainment/information devices, the demand on flash memory has been also increased radically. In general, flash memory reveals various error patterns by the devices it is mounted, and thus the memory makers are trying to minimize error ratio in the final process through not only the electric test but also the data integrity test under the same condition as real application devices. This process is called an application-level memory test. Though currently various flash memory testing devices have been used in the production lines, most of the works related to memory test depend on the sensual abilities of human testers. In case of testing the flash memory for MP3 devices, the human testers are checking if the memory has some errors by hearing the audio played on the memory testing device. The memory testing process like this has become a bottleneck in the flash memory production line. In this paper, we propose an audio comparison technique to support the efficient flash memory test for MP3 devices. The technique proposed in this paper compares the variance change rate between the source binary file and the decoded analog signal and checks automatically if the memory errors are occurred or not.