• Progress in Medical Physics
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• v.15 no.4
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• pp.202-209
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• 2004

Flat panel based digital radiography (DR) systems have recently become useful and important in the field of diagnostic radiology. For DRs with amorphous silicon photosensors, CsI(TI) is normally used as the scintillator, which produces visible light corresponding to the absorbed radiation energy. The visible light photons are converted into electric signal in the amorphous silicon photodiodes which constitute a two dimensional array. In order to produce good quality images, detailed behaviors of DR detectors to radiation must be studied. The relationship between air exposure and the DR outputs has been investigated in many studies. But this relationship was investigated under the condition of the fixed tube voltage. In this study, we investigated the relationship between the DR outputs and X-ray in terms of the absorbed energy in the detector rather than the air exposure using SPEC-l8, an X-ray energy spectrum model. Measured exposure was compared with calculated exposure for obtaining the inherent filtration that is a important input variable of SPEC-l8. The absorbed energy in the detector was calculated using algorithm of calculating the absorbed energy in the material and pixel values of real images under various conditions was obtained. The characteristic curve was obtained using the relationship of two parameter and the results were verified using phantoms made of water and aluminum. The pixel values of the phantom image were estimated and compared with the characteristic curve under various conditions. It was found that the relationship between the DR outputs and the absorbed energy in the detector was almost linear. In a experiment using the phantoms, the estimated pixel values agreed with the characteristic curve, although the effect of scattered photons introduced some errors. However, effect of a scattered X-ray must be studied because it was not included in the calculation algorithm. The result of this study can provide useful information about a pre-processing of digital radiography.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.44-50
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• 2001

Metal oxide semiconductor (MOS) structures containing nanocrystals are fabricated by using rapid thermal oxidations of amorphous silicon films. The amorphous films are deposited either by electron beam deposition method or by electron beam deposition assisted by Ar ion beam during deposition. Post oxidation of e-beam deposited film results in relatively small hysteresis of capacitance-voltage (C-V) and the flat band voltage shift, $\DeltaV_{FB}$ is less than 1V indicative of the formation of low density nanocrystals in $SiO_2$ near $SiO_2$/Si interface. By contrast, we observe very large hysteresis in C-V characteristics for oxidized ion-beam assisted e-beam deposited sample. The flat band voltage shift is larger than 22V and the hysteresis becomes even broader as increasing injection times of holes at accumulation condition and electrons at inversion condition. The result indicates the formation of slow traps in $SiO_2$ near $SiO_2$/Si interface which might be related to large density nanocrystals. Roughly estimated trap density is $1{\times}10^{13}cm^{-2}$. Such a large hysteresis may be explained in terms of the activation of adatom migration by Ar ion during deposition. The activated migration may increase nucleation rate of Si nuclei in amorphous Si matrix. During post oxidation process, nuclei grow into nanocrystals. Therefore, ion beam assistance during deposition may be very feasible for MOS structure containing nanocrystals with large density which is a basic building block for single electron memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.115-116
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• 2012

The demand for flexible electronic systems such as wearable computers, E-paper, and flexible displays has increased due to their advantages of excellent portability, conformal contact with curved surfaces, light weight, and human friendly interfaces over present rigid electronic systems. This seminar introduces three recent progresses that can extend the application of high performance flexible inorganic electronics. The first part of this seminar will introduce a RRAM with a one transistor-one memristor (1T-1M) arrays on flexible substrates. Flexible memory is an essential part of electronics for data processing, storage, and radio frequency (RF) communication and thus a key element to realize such flexible electronic systems. Although several emerging memory technologies, including resistive switching memory, have been proposed, the cell-to-cell interference issue has to be overcome for flexible and high performance nonvolatile memory applications. The cell-to-cell interference between neighbouring memory cells occurs due to leakage current paths through adjacent low resistance state cells and induces not only unnecessary power consumption but also a misreading problem, a fatal obstacle in memory operation. To fabricate a fully functional flexible memory and prevent these unwanted effects, we integrated high performance flexible single crystal silicon transistors with an amorphous titanium oxide (a-TiO2) based memristor to control the logic state of memory. The $8{\times}8$ NOR type 1T-1M RRAM demonstrated the first random access memory operation on flexible substrates by controlling each memory unit cell independently. The second part of the seminar will discuss the flexible GaN LED on LCP substrates for implantable biosensor. Inorganic III-V light emitting diodes (LEDs) have superior characteristics, such as long-term stability, high efficiency, and strong brightness compared to conventional incandescent lamps and OLED. However, due to the brittle property of bulk inorganic semiconductor materials, III-V LED limits its applications in the field of high performance flexible electronics. This seminar introduces the first flexible and implantable GaN LED on plastic substrates that is transferred from bulk GaN on Si substrates. The superb properties of the flexible GaN thin film in terms of its wide band gap and high efficiency enable the dramatic extension of not only consumer electronic applications but also the biosensing scale. The flexible white LEDs are demonstrated for the feasibility of using a white light source for future flexible BLU devices. Finally a water-resist and a biocompatible PTFE-coated flexible LED biosensor can detect PSA at a detection limit of 1 ng/mL. These results show that the nitride-based flexible LED can be used as the future flexible display technology and a type of implantable LED biosensor for a therapy tool. The final part of this seminar will introduce a highly efficient and printable BaTiO3 thin film nanogenerator on plastic substrates. Energy harvesting technologies converting external biomechanical energy sources (such as heart beat, blood flow, muscle stretching and animal movements) into electrical energy is recently a highly demanding issue in the materials science community. Herein, we describe procedure suitable for generating and printing a lead-free microstructured BaTiO3 thin film nanogenerator on plastic substrates to overcome limitations appeared in conventional flexible ferroelectric devices. Flexible BaTiO3 thin film nanogenerator was fabricated and the piezoelectric properties and mechanically stability of ferroelectric devices were characterized. From the results, we demonstrate the highly efficient and stable performance of BaTiO3 thin film nanogenerator.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.311-311
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• 2016

최근 고성능 디스플레이 개발이 요구되면서 기존 비정질 실리콘(a-Si)을 대체할 산화물 반도체에 대한 연구 관심이 급증하고 있다. 여러 종류의 산화물 반도체 중 a-IGZO (amorphous indium-gallium-zinc oxide)가 높은 전계효과 이동도, 저온 공정, 넓은 밴드갭으로 인한 투명성 등의 장점을 가지며 가장 연구가 활발하게 보고되고 있다. 기존에는 SG(단일 게이트) TFT가 주로 제작 되었지만 본 연구에서는 DG(이중 게이트) 구조를 적용하여 고성능의 a-IGZO 기반 박막 트랜지스터(TFT)를 구현하였다. SG mode에서는 하나의 게이트가 채널 전체 영역을 제어하지만, double gate mode에서는 상, 하부 두 개의 게이트가 동시에 채널 영역을 제어하기 때문에 채널층의 형성이 빠르게 이루어지고, 이는 TFT 스위칭 속도를 향상시킨다. 또한, 상호 모듈레이션 효과로 인해 S.S(subthreshold swing)값이 낮아질 뿐만 아니라, 상(TG), 하부 게이트(BG) 절연막의 계면 산란 현상이 줄어들기 때문에 이동도가 향상되고 누설전류 감소 및 안정성이 향상되는 효과를 얻을 수 있다. Dual gate mode로 동작을 시키면, TG(BG)에는 일정한 positive(or negative)전압을 인가하면서 BG(TG)에 전압을 가해주게 된다. 이 때, 소자의 채널층은 depletion(or enhancement) mode로 동작하여 다른 전기적인 특성에는 영향을 미치지 않으면서 문턱 전압을 쉽게 조절 할 수 있는 장점도 있다. 제작된 소자는 p-type bulk silicon 위에 thermal SiO2 산화막이 100 nm 형성된 기판을 사용하였다. 표준 RCA 클리닝을 진행한 후 BG 형성을 위해 150 nm 두께의 ITO를 증착하고, BG 절연막으로 두께의 SiO2를 300 nm 증착하였다. 이 후, 채널층 형성을 위하여 50 nm 두께의 a-IGZO를 증착하였고, 소스/드레인(S/D) 전극은 BG와 동일한 조건으로 ITO 100 nm를 증착하였다. TG 절연막은 BG 절연막과 동일한 조건에서 SiO2를 50 nm 증착하였다. TG는 S/D 증착 조건과 동일한 조건에서, 150 nm 두께로 증착 하였다. 전극 물질과, 절연막 물질은 모두 RF magnetron sputter를 이용하여 증착되었고, 또한 모든 patterning 과정은 표준 photolithography, wet etching, lift-off 공정을 통하여 이루어졌다. 후속 열처리 공정으로 퍼니스에서 질소 가스 분위기, $300^{\circ}C$ 온도에서 30 분 동안 진행하였다. 결과적으로 $9.06cm2/V{\cdot}s$, 255.7 mV/dec, $1.8{\times}106$의 전계효과 이동도, S.S, on-off ratio값을 갖는 SG와 비교하여 double gate mode에서는 $51.3cm2/V{\cdot}s$, 110.7 mV/dec, $3.2{\times}108$의 값을 나타내며 훌륭한 전기적 특성을 보였고, dual gate mode에서는 약 5.22의 coupling ratio를 나타내었다. 따라서 산화물 반도체 a-IGZO TFT의 이중게이트 구조는 우수한 전기적 특성을 나타내며 차세대 디스플레이 시장에서 훌륭한 역할을 할 것으로 기대된다.

• Korean Journal of Materials Research
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• v.19 no.2
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• pp.61-67
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• 2009

Electrolessly deposited Co (Re,P) was investigated as a possible capping layer for Cu wires. 50 nm Co (Re,P) films were deposited on Cu/Ti-coated silicon wafers which acted as a catalytic seed and an adhesion layer, respectively. To obtain the optimized bath composition, electroless deposition was studied through an electrochemical approach via a linear sweep voltammetry analysis. The results of using this method showed that the best deposition conditions were a $CoSO_4$ concentration of 0.082 mol/l, a solution pH of 9, a $KReO_4$ concentration of 0.0003 mol/l and sodium hypophosphite concentration of 0.1 mol/L at $80^{\circ}C$. The thermal stability of the Co (Re,P) layer as a barrier preventing Cu was evaluated using Auger electron spectroscopy and a Scanning calorimeter. The measurement results showed that Re impurities stabilized the h.c.p. phase up to $550^{\circ}C$ and that the Co (Re,P) film efficiently blocked Cu diffusion under an annealing temperature of $400^{\circ}C$ for 1hr. The good barrier properties that were observed can be explained by the nano-sized grains along with the blocking effect of the impurities at the fast diffusion path of the grain boundaries. The transformation temperature from the amorphous to crystal structure is increased by doping the Re.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.105.2-105.2
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• 2011

화비정질 실리콘의 빛에 의한 노화현상 (light-induced degradation; LID)은 이미 1977년 보고된 Staebler-Wronski 효과에 의해서 확인된 바 있다. 이는 비정질 실리콘이 빛에 노출될 때, 이미 포함되어 있는 수소원자가 빛 에너지에 의해서 이동하게 되고, 이로 인해서 생성 또는 소멸되는 댕글링 본드 때문에 일어난다. 특히, 일상적인 태양광의 노출 하에서 태양전지의 장시간 성능을 예측하는데 물리적인 이해의 부족 및 기술 환경적인 어려움이 있고, 이러한 요인들은 안정된 태양전지를 개발하는데 장해요인으로 나타난다. 그러므로 비정질 실리콘 태양전지가 장시간 태양광에 노출되어 시간이 지남에 따라서 "성능이 어떻게 변하는지?" 그리고 "이에 대한 원인은 무엇인지?" 등은 여전히 과학적으로 풀어야할 숙제로 남아있다. 본 논문에서는 비정질 실리콘으로 구성된 태양전지가 태양광에 노출될 때 시간이 지남에 따라서 (1) 성능이 어떻게 변하는지, (2) LID의 변화는 언제 안정화되는지, 그리고 (3) 성능변화에 대한 원인은 무엇인지에 대해서 논의한다. 본 논문은 장시간 빛에 노출되는 비정질 실리콘 태양전지의 성능예측에 관해서 연구하였다. 결함밀도의 운동학적 모형을 통해서 태양광 노출에 대한 태양전지 성능변화를 예측하는데 초점을 맞추었고, 이를 위해서 태양전지에 조사되는 태양광 세기, 주변온도, 등이 고려되었다. 특히, 전하운반자의 수명이 결함밀도에 의해서 결정되기 때문에 비정질 실리콘 태양전지의 빛에 대한 노화현상 (LID)이 확장지수함수 (stretched-exponential) 완화법칙을 따르는 결함밀도에 의해서 물리적으로 설명된다. 한편 이와 같은 물리적 계산의 유용성을 확인하기 위해서 동일한 태양전지에 대해서 AMPS-1D 컴퓨터 프로그램을 사용하였고, 이를 통해서 비정질 실리콘 태양전지의 빛에 대한 노화현상을 물리적 및 정량적으로 이해하였다. 본 연구에 적용되는 태양전지는 비정질 실리콘으로 구성된 pin 구조 (glass/$SnO_2$/a-SiC:H:B/a-Si:H/a-Si:H:P/ITO)로서 다음과 같은 특성을 갖는다: 에너지 띠간격~1.72 eV, 두께~400 nm, 내부전위~1.05 V, 초기 fill factor~0.71, 초기 단락전류~16.4 mA/$cm^2$, 초기 개방전압 0.90 V, 초기 변환효율 10.6 %. 우리는 이와 같은 연구를 통해서 과학적으로 비정질 실리콘의 빛에 의한 노화현상을 이해하고, 기술적으로 효율 및 경제성이 높은 태양전지의 개발에 도전한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.114-121
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• 2001

A circuit model for active-controlled field emitter array(ACFEA) as an electron source of active-controlled field emission display(ACFED) has been proposed. The ACFEA with hydrogenated amorphous silicon thin-film transistor(a-Si:H TFT) and Spindt-type molibdenum tips (Spindt-Mo FEA) has been fabricated monolithically on the same glass. A-Si:H TFT is used as a control device of field emitters, resulting in stabilizing emission current and lowering driving voltage. The basic model parameters extracted from the electrical characteristics of the fabricated a-Si:H TFT and Spindt-Mo FEA were implemented into the ACFEA model with a circuit simulator SPICE. The accuracy of the equivalent circuit model was verified by comparing the simulated results with the measured one through DC analysis of the ACFEA. The transient analysis of the ACFEA showed that the gate capacitance of FEA along with the drivability of TFT strongly affected the response time. With the fabricated ACFEA, we obtained a response time of 15$mutextrm{s}$, which was enough to make 4bit/color gray scale with the pulse width modulation (PWM).

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.17-25
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• 1999

Tungsten nitride($WN_x$) films were deposited by PECVD method on silicon nitride($WSi_3N_4$) substrate. The characteristics of $WN_x$ film were investigated with changing various processing parameters ; substrate temperature, gas flow rate, rf power, and different nitrogen sources. The nitrogen composition in $WN_x$ film varied from 0 to 45% according to the $NH_3$ and $N_2$ flow rate. The highest deposition rate of 160 nm/min was obtained for the $NH_3$ gas and relatively low deposition rate of $WN_x$ films were formed by $N_2$ gas. $WN_x$ films deposited on $WSi_3N_4$ substrate had higher deposition rate than that of TiN and Si substrates. The purity of $WN_x$ film were analyzed by AES and higher purity $WN_x$ films were deposited using $NH_3$ gas. The XRD analysis indicates a phase transition from polycrystalline tungsten(W) to amorphous tungsten nitride($WN_x$), showing improved etching profile of $WN_x$ films Thick $WN_x$ films were deposited on various substrates such as Tin, NiCr and Al and maximum thickness of $1.6 {\mu}m$ was obtained on the Al adhesion layer.

• Journal of the Korean Ceramic Society
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• v.52 no.6
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• pp.410-416
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• 2015

Recently, a new $Y_2O_3$ coating deposited using the EB-PVD method has been developed for erosion resistant applications in fluorocarbon plasma environments. In this study, surface crack formation in the $Y_2O_3$ coating has been analyzed in terms of residual stress and elastic modulus. The coating, deposited on silicon substrate at temperatures higher than $600^{\circ}C$, showed itself to be sound, without surface cracks. When the residual stress of the coating was measured using the Stoney formula, it was found to be considerably lower than the value calculated using the elastic modulus and thermal expansion coefficient of bulk $Y_2O_3$. In addition, amorphous $SiO_2$ and crystalline $Al_2O_3$ coatings were similarly prepared and their residual stresses were compared to the calculated values. From nano-indentation measurement, the elastic modulus of the $Y_2O_3$ coating in the direction parallel to the coating surface was found to be lower than that in the normal direction. The lower modulus in the parallel direction was confirmed independently using the load-deflection curves of a micro-cantilever made of $Y_2O_3$ coating and from the average residual stress-temperature curve of the coated sample. The elastic modulus in these experiments was around 33 ~ 35 GPa, which is much lower than that of a sintered bulk sample. Thus, this low elastic modulus, which may come from the columnar feather-like structure of the coating, contributed to decreasing the average residual tensile stress. Finally, in terms of toughness and thermal cycling stability, the implications of the lowered elastic modulus are discussed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.30-37
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• 1989

The PIN type a-SiC:H/a-Si:H heterojunction solar cells were fabricated by using the rf glow discharge decomposition of $SiH_4$ mixed with $CH_4,B_2,H_6\;and\;PH_3.$ The efficiency of the solar cell of the $SnO_2/ITO$ was higher than that of ITO transparent oxide layer by 1.5%. The P layer was prepared with the thickness of $100{\AA}$ and $CH_4/SiH_4$ ration of 5. The I layer has been deposited on the P layer and it is not pure intrinsic but near N type. So $SiH_4$ mixed with $B_2H_6$ of 0.3ppm was used to change this N type nature to intrinsic having the thickness of 5000${\AA}$. And consecutively, the N layer was deposited with t ethickness of $400{\AA}$ using $SiH_4/PH_3$ mixtures. The solar cell demonstrated 0.94V of $V_{oc'}$ 14.6mA/cm of $J_{sc}$ and 58.2% of FF, resulting the efficiency of 8.0%. To minimize loss by the reflection of light, $MgF_2$ layer was coated on the lgass and the efficiency was improved by 0.5%. Therefore, the solar cell indicated overall efficiency of 8.5%.