• E2M - 전기 전자와 첨단 소재
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• 제11권11호
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• pp.22-27
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• 1998

We have investigated the effect of an ion shower doping of the laser annealed poly-Si films at an elevated substrate temperatures. The substrate temperature was varied from room temperature to 300$^{\circ}C$ when the poly-Si film was doped with phosphorus by a non-mass-separated ion shower. Optical, structural, and electrical characterizations have been performed in order to study the effect of the ion showering doping. The sheet resistance of the doped poly-Si films was decreased from7${\times}$106 $\Omega$/$\square$ to 700 $\Omega$/$\square$ when the substrate temperature was increased from room temperature to 300$^{\circ}C$. This low sheet resistance is due to the fact that the doped film doesn't become amorphous but remains in the polycrystalline phase. The mildly elevated substrate temperature appears to reduce ion damages incurred in poly-Si films during ion-shower doping. Using the ion-shower doping at 250$^{\circ}C$, the field effect mobility of 120 $\textrm{cm}^2$/(v$.$s) has been obtained for the n-channel poly-Si TFTs.

• 대한전자공학회논문지SD
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• 제40권7호
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• pp.481-485
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• 2003

25㎛ 두께의 폴리이미드 박핀 기판을 glass 기판에 부착하여 최대 온도 150℃에서 비정질 실리콘 TFT를 제작하였다. 본 논문은 plastic 기판 위에 TFT가 제작되는 공정 절차를 요약하고 glass 위에 제작된 TFT와 ON/OFF 전달특성과 전계효과 이동도를 서로 비교해 보았다. a-SiN:H 코팅층은 plastic 기판의 표면 거칠기를 감소시키는 중요한 역할을 하여 TFT의 누설전류를 감소시키고 전계효과 이동도를 증가시켰다. 따라서 a-SiN:H 코팅층을 이용하여 plastic 기판에 양철의 TFT를 제작하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.733-740
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• 2014

A resistive micro Pirani gauge using amorphous silicon (a-Si) thin membrane is proposed. The proposed Pirani gauge can be easily integrated with the other process-compatible membrane-type sensors, and can be applicable for in-situ vacuum monitoring inside the vacuum package without an additional process. The vacuum level is measured by the resistance changes of the membrane using the low noise correlated double sampling (CDS) capacitive trans-impedance amplifier (CTIA). The measured vacuum range of the Pirani gauge is 0.1 to 10 Torr. The sensitivity and non-linearity are measured to be 78 mV / Torr and 0.5% in the pressure range of 0.1 to 10 Torr. The output noise level is measured to be $268{\mu}V_{rms}$ in 0.5 Hz to 50 Hz, which is 41.2% smaller than conventional CTIA.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.37-37
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• 2008

Hydrogenated nanocrystalline Si (nc-Si:H) thin films were prepared by plasma enhanced chemical vapor deposition (PECVD). The films were deposited with a radio frequency power of 100 W, while substrates were exposed to direct current (DC) biases in the range from 0 to -400 V. The effects of the DC bias on the formation of nanoscale Si crystallites in the films and on their optical characteristics were investigated. The size of the Si crystallites in the films ranges from ~ 1.9 to ~ 4.1 nm. The relative fraction of the crystallites in the films reached up ~ 56.5 % when the DC bias of -400 V was applied. Based on the variation in the structural, chemical, and optical features of the films with DC bias voltages, a model for the formation of nanostructures of the nc-Si:H films prepared by PECVD was suggested. This model can be utilized to understand the evolution in the size and relative fraction of the nanocrystallites as well as the amorphous matrix in the nc-Si:H films.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.708-711
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• 1999

The Cu/Ni/Au lamellar structure is extensively used as an under bump metallization on silicon file, and on printed circuit board(PCB) pads. Ni is plated Cu by either electroless Ni plating, or electrolytic Ni plating. Unlike the electrolytic Ni plating, the electroless Ni plating does not deposit pure Ni, but a mixture of Ni and phosphorous, because hypophosphite Is used in the chemical reaction for reducing Ni ions. The fracture crack extended at the interface between solder balls of plastic ball grid (PBGA) package and conducting pads of PCB. The fracture is duets to segregation at the interface between Ni$_3$Sn$_4$intermetallic and Ni-P layer. The XPS diffraction results of Cu/Ni/Au results of CU/Ni/AU finishs showed that the Ni was amorphous with supersaturated P. The XPS and EDXA results of the fracture surface indicated that both of the fracture occurred on the transition lesion where Sn, P and Ni concentrations changed.

• Journal of Information Display
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• 제7권3호
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• pp.1-4
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• 2006

2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (a-Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated as the 2.5 um fine pattern formation technique is integrated with high thermal photo-resist (PR) development. In addition, a novel concept of unique a-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um fine-patterning is a considerably significant technology to obtain higher aperture ratio for higher resolution a-Si TFT-LCD panel realization.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권5호
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• pp.315-318
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• 1999

We have proposed and fabricated the new bottom-gated polycrystalline silicon (poly-Si) thin film transistor (TFT) with a partial amorphous-Si region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the ON/OFF current ratio is increased significantly by more than three orders in the new poly-Si TFT compared with conventional poly-Si TFT. The leakage current is decreased significantly due to the highly resistive a-Si re TFTs while the ON-series resistance of the local a-Si is reduced significantly due to the considerable inducement of electron carriers by the positive gate bias, so that the ON-current is not decreased much.

• 한국전기전자재료학회논문지
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• 제29권6호
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• pp.376-379
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• 2016

In this paper, the efficiency improvement of the heterojunction with intrinsic thin layer (HIT) solar cells is obtained by optimization process of p-type a-SiC:H as emitter. The optoelectronic of p-type a-SiC:H layers including the optical band-gap and conductivity under the methane gas content variation is conducted in detail. A significant increase in the Jsc by $1mA/cm^2$ and Voc by 30 mV are attributed to enhanced photon-absorption due to broader band-gap of p-a-SiC:H and reduced band-offsets at p-side interface, respectively of HIT solar cells.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1147-1149
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• 1993

ZnO/$SnO_2$:F bilayer films have been prepared by pyrosol deposition method to develop optimum transparent electrode for use in amorphous silicon solar cells. The solution for $SnO_2:F$ film was composed of $SnCl_4{\cdot}5H_2O,\;NH_4F,\;CH_3OH$ and HCl, and ZnO films have been deposited on the $SnO_2:F$ films by using the solution of $ZnO(CH_3COO){_2}{\cdot}2H_2O,\;H_2O\;and\;CH_3OH$. These films have been investigated the variation of electrical and optical properties under the hydrogen plasma exposure. The sheet resistance of the $SnO_2:F$ film was sharply increased and its transmittance was decreased with the blackish effect after plasma treatment. However, the ZnO/$SnO_2:F$ bilayer film was shown hydrogen plasma durability because the electrical and optical properties was almost unchanged more then 60 seconds exposure time.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.207.2-207.2
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• 2013

Oxide-based thin film transistors have been attempted as powerful candidates for driving circuits for active-matrix organic light-emitting diodes and transparent electronics. The oxide TFTs are based on the amorphous multi-component oxides involving zinc, indium, and/or tin elements as main cation sources. The current work employed RF sputtering in order to deposit zinc-tin oxide thin films applicable to transparent oxide thin film transistors. The deposited thin film was characterized and probed in terms of materials and devices. The physical/chemical characterizations were performed using X-ray diffraction, Atomic Force Microscopy, Spectroscopic Ellipsometry, and X-ray Photoelectron Spectroscopy. The thin film transistors were fabricated using a bottom-gated structure where thermally-grown silicon oxide layers were applied as gate-dielectric materials. The inherent properties of oxide thin films are combined with the corresponding device performances with the aim to fabricating the multi-component oxide thin films being optimized towards transparent electronics.