• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.38-48
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• 1993

A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.193-193
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• 2013

실리콘 박막 태양전지는 광 흡수층에서 형성된 정공과 전자를 효과적으로 분리하기 위해 p형과 n형으로 도핑된 층을 형성하는 p-i-n구조를 갖게 된다. 이러한 도핑 층을 형성하기 위해 B2H6와 PH3와 같은 독성 가스를 사용하기 때문에, 공정 안정성과 환경적인 이슈가 대두된다. 또한 도핑은 추가적으로 실리콘 박막 태양전지의 안정화 효율을 지속적으로 저하시키는 요인이 된다. 이러한 문제점을 개선하기 위하여, 창층으로 MoO3, V2O5, WO3 등과 같이 높은 일함수를 갖는 전이금속 산화물을 사용하고, 광 흡수층으로 i-Si:H을, 후면 전극으로 낮은 일함수를 나타내는 LiF/Al을 사용하였다. 전이금속 산화물과 LiF/Al의 큰 일함수 차이에 의해서 흡수층인 i-Si:H 에서 생성된 캐리어들은 효과적으로 분리되고 수집이 된다. 금속 산화물은 스퍼터링 공정에 의하여 이루어졌으며, 스퍼터링 공정조건에 따라 산화도가 조절되며, 이러한 산화도에 따라 태양전지의 셀 특성이 결정된다. 도핑 층이 없는 새로운 형태의 실리콘 박막 태양전지는 기존 비정질 실리콘 박막 태양전지에 비해 높은 안정화 효율을 나타내며, 이는 도핑 층이 없기 때문에 기존 실리콘 박막 태양전지의 열화현상에 따른 효율저하가 발생하지 않는 장점을 지내고 있다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.236-242
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• 1986

The dependence of the current-voltage characteristics of hydrogenated amorphous silicon pin solar cells on the illumimination light intensity has been investigated. The open circuit voltage increases linearly with increasing the logarithm of light intensity up to AM 1, and nearly saturates above AM 1, indicating the open circuit voltage approaching the built-in potential of the pin solar cell above AM 1. The short circuit current density increase with light intensity in proportion to I**0.85 before and I**0.97 after light exposure. Since the series resistance devreses and shunt resistance increases with light intensily, the fill factor increases with light illumination. To increase the fill factor at high illumination in large area solar cells, t6he grid pattern on the ITO substrates should be made. Long light exposure on the solar cells gives rise to the increase of bulk resistance and defect states, resulting in the decrease of the fil factor and short circuit current density. The potential drop in the bulk of the a-Si:H pin solar cells at short circuit condition increases with decreasing temperature, and increases after long light exposure.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.1-5
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• 2006

We prepared 80 nm-thick TiSix on each 70 nm-thick amorphous silicon and polysilicon substrate using an RF sputtering with $TiSi_2$ target. TiSix composite silicide layers were stabilized by rapid thermal annealing(RTA) of $800^{\circ}C$ for 20 seconds. Line width of $0.5{\mu}m$ patterns were embodied by photolithography and dry etching process, then each additional annealing process at $750^{\circ}C\;and\;850^{\circ}C$ for 3 hours was executed. We investigated the change of sheet resistance with a four-point probe, and cross sectional microstructure with a field emission scanning electron microscope(FE-SEM) and transmission electron microscope(TEM), respectively. We observe an abrupt change of resistivity and voids at the silicide surface due to interdiffusion of silicide and composite titanium silicide in the amorphous substrates with additional $850^{\circ}C$ annealing. Our result implies that the electrical resistance of composite titanium silicide may be tunned by employing appropriate substrates and annealing condition.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.82-82
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• 2015

Industrial crystalline silicon (c-Si) solar cells with using a screen printing technology share the global market over 90% and they will continue to be the same for at least the next decade. It seems that the $2^{nd}$ generation and the $3^{rd}$ generation technologies have not yet demonstrated competitiveness in terms of performance and cost. In 2014, new world record efficiency 25.6% (Area-$143.7cm^2$, Voc-0.740V, $Jsc-41.8mA/cm^2$, FF-0.827) was announced from Panasonic and its cell structure is Back Contact $HIT^*$ c-Si solar cell. Here, amorphous silicon passivated contacts were newly applied to back contact solar cell. On the other hand, 24.9% $TOPCon^{**}$ cell was announced from Fraunhofer ISE and its key technology is an excellent passivation quality applying tunnel oxide (<2 nm) between metal and silicon or emitter and base. As a result, to realize high efficiency, high functional technologies are quite required to overcome a theoretical limitation of c-Si solar cell efficiency. In this presentation, Si solar cell technology summarized in the International Technology Roadmap for Photovoltaics ($^{***}ITRPV$ 2014) is introduced, and the present status of R&D associated with various c-Si solar cell technologies will be reviewed. In addition, national R&D projects of c-Si solar cells to be performed by Korea University are shown briefly.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.44.2-44.2
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• 2009

Polycrystalline materials suchas yttria and alumina have been applied as a plasma resisting material for the plasma processing chamber. However, polycrystal line material may easily generate particles and the particles are sources of contamination during the plasma enhanced process. Amorphous material can be suitable to prevent particle generation due to absence of grain-boundaries. We manufactured nitrogen-containing $SiO_2-Al_2O_3-Y_2O_3$ based glasses with various contents of silicon and fixed nitrogen content. The thermal properties, mechanical properties and plasma etching rate were evaluated and compared for the different composition samples. The plasma etching behavior was estimated using XPS with depth profiling. From the result, the plasma etching rate highly depends on the silicon content and it may results from very low volatile temperature of SiF4 generated during plasma etching. The silicon concentration at the plasma etched surface was very low besides the concentration of yttrium and aluminum was relatively high than that of silicon due to high volatile temperature of fluorine compounds which consisted with aluminum and yttrium. Therefore, we conclude that the samples having low silicon content should be considered to obtain low plasma etching rate for the plasma resisting material.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.785-789
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• 2005

Low temperature deposition of silicon and silicon nitride films by catalytic CVD technique was studied for application to thin film transistors on plastic substrates for flexible AMOLEDs. The substrate temperature initially held at room temperature, and was controlled successfully below $150^{\circ}C$ during the entire deposition process. Amorphous silicon films having good adhesion, good surface morphology and sufficiently low content of atomic hydrogen were obtained and could be successfully crystallized using excimer laser without a prior dehydrogenation step. $SiN_x$ films showed a good refractive index, a high deposition rate, a moderate breakdown field and a dielectric constant. The Cat-CVD silicon and silicon nitride films can be good candidates for fabricating thin films transistors on plastic substrates to drive active-matrix organic light emitting display.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.750-758
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• 2016

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.30-40
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• 1998

We have calculated ultra-low energy silicon-self ion implantations and silicon damages through classical molecular dynamics simulation using empirical potentials. We tested whether the recently developed Environment-Dependent Interatomic Potential(EDIP) was suitable for ultra low energy ion implantation simulation, and found that point defects formation energies were in good agreement with other theoretical calculations, but the calculated vacancy migration energy was overestimated. Most of the damages that are produced by collision cascades are concentrated into amorphous-like pockets. Also, We upgraded MDRANGE code for silicon ion implantation process simulation. We simulated ultra-low energy boron ion implantation, 200eV, 500eV, and 1000eV respectively, and calculated boron profiles with silicon substrate temperature and tilt angle. We investigated that below 1000eV, channeling effect must be considered.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.5 no.3
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• pp.299-305
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• 1995

Visible photoluminescing (PL) silicon at room temperature has been prepared by a dry technique, that is, by spark processing, contrary to anodically etched porous silicon. PL peak maximum of photoluminescing spark processed Si was shifted to blue 520 nm. The stability of spark processed Si towards degradation upon UV radiation was found to be extremely high. Results from high resolution TEM, XRD and XPS studies suggest that spark processed silicon involves minute nanocrystalline (polycrystalline) particles which are imbedded in an amorphous matrix, preferably $SiO_2$.