• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권5호
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• pp.319-325
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• 1999

Direct current(d.c.)leakage current voltage characteristics of radio-frequencymagnetron sputtered BaTa\sub 2\O\sub 6\ film capacitors with aluminum(A1) top and indium tin oxide (ITO) bottom electrodes have been investigatedas a function of applied field and temperature. In order to study surfacetreatment effect on the electrical characteristics of as-deposited film weperformed exposure of oxygen plasma on $BaTa_2O_6$ surface. d. c.current-voltage (I-V), bipolar pulse charge-voltage (Q-V), d. c. current-time (I-t) andcapacitance-frequency (C-f) analysis were performed on films. All ofthe films exhibita low leakage current, a high breakdown field strength (3MV/cm-4.5MV/cm), and high dielectric constant (20-30). From the temperature dependence of leakage current,we can conclude that the dominant conduction mechanism is ascribed toSchottky emission at high electric field (>1MV/cm) and hopping conduction at lowelectric field (<1MV/cm). According to our results, the oxide plasma surfacetreatmenton as-deposited $BaTa_2O_6$ resulted in lowering interfacebarrier height and thus, leakage current when a negative voltage applied to the A1 electrode. This can be explained by reduction of surface contamination via etching surface and filling defects such as oxygen vacancies.

• 한국전기전자재료학회논문지
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• 제22권6호
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• pp.470-475
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• 2009

We deposited $Al_2O_3$ thin films on GaN by remote plasma atomic layer deposition (RPALD) technique, trimethylaluminum(TMA) and oxygen were used as precursors, at fixed process condition, the number of cycle were changed. Growth rate per cycle was $1.2\;{\AA}$/cycle. and Growth rate was in proportion to a number of cycle, the GaN MIS capacitors that $Al_2O_3$ thin film were deposited above 12 nm, have excellent electrical properties, a low electrical leakage current density(${\sim}10^{-10}\;A/cm^2$ at 1.5 MV), but below 12 nm, we can see the degradation of the leakage current density. After post deposition annealing, Dielectric constant was estimated by 1 MHz high-frequency C-V method, it was varied with the anealing temperature from 6.9 at no post anealed to 7.6 at $800^{\circ}C$, and we can see a improvement of the leakage current density and breakdown voltage by post deposition anealing below $700^{\circ}C$, but, after anealed at $800^{\circ}C$, we can see the degradation of the leakage current density and breakdown voltage.

• 한국재료학회지
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• 제4권7호
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• pp.759-766
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• 1994

본 연구에서는 Ta 박막 밑에 $SnO_{2}$박막층을 입혀서 $Ta/SnO_2$이중박막이 산화될 때 산소의 공급원을 2원화 함으로써 $Ta_2O_5$의 stoichiomitry를 향상시켜 $Ta_2O_5$박막 커패시터의 주설전류를 줄이고자 하였다. Tantalum을 실리콘 웨이퍼 위에 기판온도를 변화시켜 가면서 전자빔증착이나 스퍼터링 방밥으로 입히고 $500^{\circ}C$~$900^{\circ}C$에서 산화시켜 Al/$Ta_2O_5$p-Si/Al또는Al/$Ta_2O_5$/p-Si/Al과 같은 MIS형 커패시터를 만들어 유전상수 및 누설전류를 측정하였으며 XRD, AES, ESCA등을 이용하여 박막의 결정성 및 특성을 분석하였다. $SnO_{2}$박막층을 입힌 커패시터는$SnO_{2}$층을 입히지 않은 커패시터보다 10배 이상 큰 200정도의 유전상수 값을 나타내었다. 그리고 산화온도가 높으면 박막의 결정화로 인하여 유전상수는 증가하지아는 누설전류도 약간 증가하는 것이 확인되었다. 또한 높은 증착온도는 일반적으로 누설전류를 낮추는 것으로 나타났다. 특히 $SnO_{2}$층을 입힌 경우에 기판온도를 $200^{\circ}C$로 하고 $800^{\circ}C$에서 산화시켜 만든 커패스터의 경우에 $4 \times 10^{5}$V/cm의 전장강도에서 $10^{-7}A/\textrm{cm}^2$의 낮은 누설전류 값을 나타내었다. $Ta_2O_5$박막은 $700^{\circ}C$ 이상에서 박막이 결정되고, Ta /$SnO_{2}$ 이중박막을 산화시키면 처음에는 Ta박막과 $SnO_{2}$박막 계면에서 $SnO_{2}$로부터 Ta박막에 산소가 공급되지마는 점차 Sn이 Ta박막쪽으로 확산되어 결국에는 Ta-Sn-O계의 새로운 ternary oxide가 생성되는 것으로 나타났다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.