• Journal of the Korean institute of surface engineering
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• v.54 no.5
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• pp.285-293
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• 2021

High-entropy TiAlCrSiN nano-composite coating was designed to improve mold life for high temperature liquid molding. Alloy design, powder fabrication and single alloying target fabrication for the high-entropy nano-composite coating were carried out. Using the single alloying target, an arc ion plating method was applied to prepare a TiAlCrSiN nano-composite coating had a 30 nm TiAlCrSiN layers are deposited layer by layer, and form about 4 ㎛-thickness of multi-layered coating. TiAlCrSiN nano-composite coating had a high hardness of about 39.9 GPa and a low coefficient of friction of less than about 0.47 in a dry environment. In addition, there was no change in the structure of the coating after the dissolution loss test in the molten metal at a temperature of about 1100 degrees.

• Journal of the Korean Applied Science and Technology
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• v.16 no.4
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• pp.307-311
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• 1999

Interfacial properties of electrode and organic thin layer is one of the most important factor in performing a Light Emitting Diodes(LED). Phthalocyanine copper was used as a buffer layer to improve interface characteristic, so that device efficiency was improved. In this study, LEDs were fabricated as like structures of Indium-Tin-Oxide (ITO) / N,N' -Diphenyl-N,N'-di(m-tolyl)-benzidine (TPD) / 8-Hydroxyquinoline aluminum(Alq) / Aluminum(Al) and Indium-Tin-Oxide(ITO) / N,N'-Diphenyl-N,N' -di(m-tolyl)-benzidine(TPD) / 2-(4-Biphenylyl)-5(4-tert-butyl-phenyl)-1,3,4-oxadiazole(PBD) / Aluminum(Al). In these devices, CuPC was layered at electrode/organic layer interface. As position is changing and thickness is changing, devices showed characteristic luminescence efficiency and luminescence inensity respectively. We showed in this study that luminescence efficiency was improved with CuPC layer in LEDs. The efficiency of device with layer CuPC is higher than that of 2 layer CuPC. However, the luminescence of 2 layer CuPC device got higher value.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1321-1323
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• 1998

We investigated drain leakage current in GaAs power MESFET. The device we studied by 20 simulation has a $1000{\AA}$ thick AlGaAs buffer layer under n-GaAs active layer. The calculation shows that the leakage current through GaAs substrate is significantly reduced by the buffer layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.260-260
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• 2016

최근 고화질 및 대용량 영상의 등장으로 메모리 디바이스에 대한 연구가 활발하다. 메모리 디바이스의 oxide 층은 tunnel layer, trap layer와 blocking layer로 나누어지며, tunnel layer와 trap layer 사이 계면의 상태는 메모리 특성에 큰 영향을 준다. 한편, AlOx는 메모리 디바이스의 tunnel layer에 주로 적용되는 물질로서, AlOx를 형성하는 방법에는 진공공정을 이용하여 증착하는 방법과 알루미늄을 산화시켜 형성하는 방법이 있다. 그 중, 진공공정 방법인 RF 스퍼터를 이용하는 방법은 증착시 sputtering으로 인하여 표면에 손상을 주게 되어, 산화시켜 형성한 AlOx에 비해 막질이 좋지 않다는 단점이 있다. 따라서 본 연구에서는 우수한 막질의 메모리 디바이스를 제작하기 위하여 산화시켜 형성한 AlOx를 tunnel layer로 적용시킨 MOSCAP을 제작하여 메모리 특성을 평가하였다. 제작된 소자는 n-Si (1-20 ohm-cm) 기판을 사용하였다. Tunnel layer는 e-beam evaporator를 이용하여 Al을 5 nm 두께로 증착하고 퍼니스를 이용하여 O2 분위기에서 $300^{\circ}C$의 온도로 1시간 동안 산화시켜 AlOx을 형성하였으며, 비교군으로 RF 스퍼터를 이용하여 AlOx를 10 nm 두께로 증착한 소자를 같이 제작하였다. 순차적으로, trap layer와 blocking layer는 RF 스퍼터를 이용하여 각각 HfOx 30 nm와 SiOx 30 nm를 증착하였다. 마지막으로 전극 물질로는 Al을 e-beam evaporator를 이용하여 150 nm 두께로 증착하였다. 제작된 소자에서 메모리 측정을 한 결과, 같은 크기의 윈도우를 비교하였을 때 산화시킨 AlOx를 tunnel layer로 적용한 MOSCAP에서 더 적은 전압으로도 program 동작이 나타나는 것을 확인하였다. 또한 내구성을 확인하기 위해 program/erase를 103회 반복하여 endurance를 측정한 결과, 스퍼터로 증착한 AlOx를 적용한 MOSCAP에서는 24 %의 메모리 윈도우 감소가 일어난 반면에, 산화시킨 AlOx를 적용한 MOSCAP에서는 메모리 윈도우 감소가 5 % 미만으로 일어났다. 결과적으로 산화시킨 AlOx를 메모리소자의 tunnel layer로 적용한 MOSCAP에서 더 뛰어난 내구성을 나타냈으며, 추후 최적의 oxide 두께와 열처리 조건을 통해 더 뛰어난 메모리 특성을 가지는 메모리 디바이스 제작이 가능할 것으로 기대된다.

• ETRI Journal
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• v.38 no.4
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• pp.675-684
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• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• Journal of the Korean Society for Heat Treatment
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• v.9 no.3
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• pp.177-186
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• 1996

Surface alloying of Ti alloy by $CO_2$ laser is able to produce few hundred micrometers thick TiN or TiC surface-alloyed layer with high hardness on the substrate by injecting reaction gas($N_2$ or $CH_4$). Laser surface alloying by means of process control is in many applications essential in order to obtain predictable hardening layer. This research has been investigated the effect of such parameters on TiN and TiC gas alloying of Ti-6Al-4V alloy by $CO_2$ laser. The maximum surface hardness of TiN layer was obtained 1750Hv on the conditions of 0.8kW laser power, 0.8m/min scanning speed and 100% $N_2$ atmosphere. However, the maximum hardness of TiC formation layer after laser treatment was about 630Hv. As scanning speed was increased, the hardness and depth of these layers were decreased at constant laser power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.1-5
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• 2011

In this paper, we investigated the characteristics of AlGaN/GaN HEMTs to optimize their DC and RF characteristics by using a two-dimensional device simulator. First, we analyzed the variation of the DC characteristics with respect to the variation of 2DEG concentrations when varying the Al mole fraction and the thickness of the AlGaN layer. Then, we examined the variation of the RF characteristics by varying the size and the location of the gate, source and drain electrodes. When the Al mole fraction increased from 0.2 to 0.45, both the transconductance and I-V characteristics increased. On the other hand, the I-V characteristics were improved but transconductance was decreased as the thickness of the AlGaN layer increased from 10nm to 50nm. In the RF characteristics, the gate length was found to be the most influential parameter, and the RF characteristics were improved when the gate length was shorten.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1057-1061
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• 2007

In this study, we investigated the properties of ZnO thin films prepared by layer-by-layer method in RF magnetron sputtering system using AlAs and ZnO targets. Effects of $H_2O_2$ dip prior to thermal treatment were studied as well. Either n-type or p-type films were observed in our study depending on the annealing conditions. It thus indicates the feasibility of arbitrarily modifying the conductivity type. At the same time, it also implies the thermal instabilities of the film properties. Property measurements after stressing the films up to 144 hours showed that thermal variations of properties nay be suppressed by pre-treatment in 30% $H_2O_2$ for 1 min.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.13-19
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• 2001

We report on the fabrication and characterization of $Al_{0.3}Ga_{0.7}N$ HFETs with different barrier layer thickness which were grown using plasma-assisted molecular beam epitaxy (PAMBE). The barrier thickness of $Al_{0.3}Ga_{0.7}N$/GaN HFETs could be optimized in order to maximize 2 dimensional electron gas induced by piezoelectric effect without the relaxation of $Al_{0.3}Ga_{0.7}N$ layer. $Al_{0.3}Ga_{0.7}N$/GaN (20 nm/2 mm) HFET with 0.6 ${\mu}m$-long and 34 ${\mu}m$-wide gate shows saturated current density ($V_{gs}=1\;V$) of 1.155 A/mm and transconductance of 250 ms/mm, respectively. From high frequency measurement, the fabricated $Al_{0.3}Ga_{0.7}N$/GaN HFETs showed $F_t=13$ GHz and $F_{max}=48$ GHz, respectively. The uniformity of less than 5% could be obtained over the 2 inch wafer. In addition to the optimization of epi-layer structure, the relation between breakdown voltage and high frequency characteristics has been examined.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.100-102
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• 2013

Magnetron-sputtering법을 사용하여 기존에 연구하였던 CrAlN (Cr 7：Al 3)박막에 Si를 첨가하여 Si의 함량 변화에 따라 미세구조와 화학적 결합상태, 온도저항계수(TCR) 및 산화저항의 영향과 기계적특성 개선을 통한 multi-functional heater resistor layer로써의 가능성을 연구하였다. CrAlSiN 박막의 Si 함량에 변화에 따라 온도저항계수 변화를 확인하였으며 X-선 회절 분석(XRD) 패턴 분석결과 CrAlSiN 박막의 결정구조가 Bl-NaCl 구조를 가지고 있는 것을 확인하였으며 SEM과 AFM을 통한 표면 및 미세구조 분석결과 Si의 함량이 증가할수록 입자가 조밀해짐을 알 수 있었다. 최근 digital priting technology의 핵심 기술로 부각되고 있는 inkjet priting technology는 널리 태양전지뿐만 아니라 thin film process, lithography와 같은 반도체 공정 기술에 활용 할 수 있기 때문에 반도체 제조장비에도 사용되고 있으며, 현재 thermal inkjet 방식을 사용하고 있다. Inkjet printing technology는 전기 에너지를 잉크를 배출하기 위해 열에너지로 변환하는 thermal inkjet 방식을 사용하고 있는데, 이러한 thermal inkjet 방식은 기본적으로 전기저항이 필요하지만 electrical resistor layer는 잉크를 높은 온도에서 순간적으로 가열하기 때문에 부식이나 산화 등의 문제가 발생할 수 있어 이에 대한 보호층을 필요로 한다. 하지만, 고해상도, 고속 잉크젯 프린터, 대형 인쇄 등을 요구되고 있어 저 전력 중심의 잉크젯 프린터의 열효율을 방해하는 보호층 제거에 필요성이 제기되고 있다. 본 연구는 magnetron-sputtering을 사용하여 기존의 CrAlN 박막에 Si를 합성하여 anti-oxidation, corrosion resistance 그리고 low temperature coefficient of resistance 값을 갖는 multi-functional heater resistor layer로써 CrAlSiN 박막의 Si 함량에 따른 효과에 초점을 두었다. 본 실험은 CrAlN 박막에 Si 함량을 4~11 at%까지 첨가시켜 함량의 변화에 따른 특성변화를 확인하였다. 함량이 증가할수록 amorphous silicon nitride phase의 영향으로 박막의 roughness는 감소하였으며 XRD 분석결과 (111) peak의 Intensity가 감소함을 확인하였으며 SEM 관찰시 모든 박막이 columnar structure를 나타내었으며 Si함량이 증가할수록 입자가 치밀해짐을 보여주었다.Si함량이 증가할수록 CrAlN 박막에 비하여 면저항은 증가하였으며 TCR 측정결과 Si함량이 6.5 at%일 때 가장 안정한 TCR값을 나타내었다. Multi-functional heater resistor layer 역할을 하기 위해서, CrAlSiN 박막의 원소 분포, 표면 거칠기, 미세조직, 전기적 특성 등을 조사하였다. CrAlN 박막의 Si의 첨가는 크게 XRD 분석결과 주상 성장을 억제 할 수 있으며 SEM 분석을 통하여 Si 함량이 증가할수록 Si3N4 형성이 감소하며 입자크기가 작아짐을 확인하였다. 면저항의 경우 Si 함량이 증가함에 따라 높은 면저항을 나타내었으며 Si함량이 6.5 at%일 때 가장 낮은 TCR 값인 3120.53 ppm/K값을 보였다. 이 값은 상용되고 있는 heater resistor보다 높지만, CrAlSiN 박막이 더 우수한 기계적 특성을 가지고 있기 때문에 hybrid heater resistor로 적용할 수 있을 것으로 기대된다.