• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.112-116
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• 2000

In this paper, we investigated the relationship between the position of bus electrode and address time, luminance and luminous efficiency in ac PDP of 50in. XGA resolution. When the bus electrode was placed in which was about $140{\mu}m$ apart from discharge gap, the luminous efficiency was the highest and address time was the least. Whereas, when the bus electrode was placed in the edge of ITO, the luminance was the highest.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.99-109
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• 1992

First, the coupling faults of semiconductor memory are classified in detail. The chained coupling fault is introduced and defined, which results from sequential influencing of the coupling effects among memory cells, and its mapping relation is described. The linked coupling fault and its order are defined. Second, the deterministic “Algorithm GA” is proposed, which detects stuack-at faults, transition faults, address decoder faults, unlinked 2-coupling faults, and unlinked chained coupling faults. The time complexity and the fault coverage are improved in this algorithm. Third, it is proved that the march test of an address sequence can detect 97.796% of the linked 2-coupling faults with order 2. The deterministic “Algorithm NA” proposed can detect to the limit. The time complexity and the fault coverage are improved in this algorithm.

• Journal of the Korea Society of Computer and Information
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• v.22 no.12
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

• Journal of the Korea Concrete Institute
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• v.12 no.5
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• pp.153-164
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• 2000

Numerical studies were carried out to investigate long-term behavior of flat plates, subjected to combined in-plane compressive and transverse loads. For the numerical studies, a computer program of nonlinear finite element analysis was developed. It can address creep and shrinkage as weel as geometrical and material nonlinearity, and also it can address various load combinations and loading sequences of transverse load, in-plane compressive load and time. This numerical method was verified by comparison with the existing experiments. Parametric studies were performed to investigate the strength variations of flat plates with four parameters; 1) loading sequence of floor load, compressive load and time 2) uniaxial and biaxial compression 3) the ratio of dead to live load 4) span length. Through the numerical studies, the behavioral characteristics of the flat plates and the governing load combinations were examined. These results will be used to develop a design procedure for the long-term behavior of flat plates in the future.

• Journal of the Korean Operations Research and Management Science Society
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• v.27 no.2
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• pp.97-109
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• 2002

Manufacturing environments in the real world are subject to many sources of change and uncertainty, such as new job releases, job cancellations, a chance in the processing time or start time of some operation. Thus, the realistic scheduling method should Properly reflect these dynamic environment. Based on the release times of jobs, JSSP (Job Shoe Scheduling Problem) can be classified as static and dynamic scheduling problem. In this research, we mainly consider the dynamic JSSP with continually arriving jobs. The goal of this research is to develop an efficient scheduling method based on GA (Genetic Algorithm) to address dynamic JSSP. we designed scheduling method based on SGA (Sing1e Genetic Algorithm) and PGA (Parallel Genetic Algorithm) The scheduling method based on GA is extended to address dynamic JSSP. Then, This algorithms are tested for scheduling and rescheduling in dynamic JSSP. The results is compared with dispatching rule. In comparison to dispatching rule, the GA approach produces better scheduling performance.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.9
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• pp.450-453
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• 2005

A high speed address recovery technique for AC plasma display panel(PDP) is proposed. Replacing GND switch by clamping diode. the recovery speed can be increased by saving GND hold-time and switching loss due to GND switch also becomes also be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Test results with 50' HD single-scan PDP(resolution = 1366$\times$768) show that less than 3sons of recovery time is successfully accomplished and about$54\%$ of the maximum power consumption can be reduced, tracing minimum power consumption curves.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.34-44
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• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• Korean Journal of Applied Biomechanics
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• v.12 no.1
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• pp.205-219
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• 2002

This research seeks to identify the plantar pressure distribution graph and change in force in connection with effective golf drive strokes and thus to help ordinary golfers have appropriate understanding on the moving of the center of weight and learn desirable drive swing movements. To this end, we conducted surveys on five excellent golfers to analyze the plantar pressure applied when performing golf drive strokes, and suggested dynamic variables quantitatively. 1) Our research presents the desire movements as follows. For the time change in connection with the whole movement, as a golfer raises the club head horizontally low above ground from the address to the top swing, he makes a semicircle using the left elbow joint and shaft and slowly turns his body, thus lengthening the time. And, as the golfer twists the right waist from the middle swing to the impact with the head taking address movement, and does a quick movement, thus shortening the time. 2) For the change in pressure distribution by phase, to strike a strong shot with his weight imposed from the middle swing to the impact, a golfer uses centrifugal force, fixes his left foot, and makes impact. This showed greater pressure distribution on the left sole than on the right sole. 3) For the force distribution graph by phase, the force in the sole from the address to halfway swing movements is distributed to the left foot with 46% and to the right foot with 54%. And, with the starting of down swing, as the weight shifts to the left foot, the force is distributed to the left sole with 58%. Thus, during the impact and follow through movements, it is desirable for a golfer to allow his left foot to take the weight with the right foot balancing the body. 4) The maximum pressure distribution and average of the maximum force in connection with the whole movement changed as the left (foot) and right (foot) supported opposing force, and the maximum pressure distribution also showed much greater on the left sole.

• Journal of the Korean Society for Railway
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• v.11 no.4
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• pp.364-370
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• 2008

In this paper, we proposed new sensor network architecture with autonomous robots based on beacon mode and implemented real time monitoring system in real test-bed environment. The proposed scheme offers beacon based real-time scheduling for reliable association process with parent nodes and dynamically assigns network address by using NAA (Next Address Assignment) mechanism. For the large scale multi-sensor processing, our real-time monitoring system accomplished the intelligent database processing, which can generate not only the alert messages to the civilians but also process various sensing data such as fire, air, temperature and etc. Moreover, we also developed mobile robot which can support network mobility. Though the performance evaluation by using real test-bed system, we illustrate that our proposed system demonstrates promising performance for emergence monitoring systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1B
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• pp.18-28
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• 2004

Efficient hardware implementation of address lookup is one of the most important design issues of internet routers. Address lookup significantly impacts router performance since routers need to process tens-to-hundred millions of packets per second in real time. In this paper, we propose a practical IP address lookup structure based on the binary tree of prefixes of different lengths. The proposed structure produces multiple balanced trees, and hence it solve the issues due to the unbalanced binary prefix tree of the existing scheme. The proposed structure is implemented using pipelined binary search combined with a small size TCAM. Performance evaluation results show that the proposed architecture requires a 2000-entry TCAM and total 245 kbyte SRAMs to store about 30,000 prefix samples from MAE-WEST router, and an address lookup is achieved by a single memory access. The proposed scheme scales very well with both of large databases and longer addresses as in IPv6.