• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1307-1316
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• 1996

In this paper, we propose a vector quantization method which uses a dynamic address mapping based on exploring the high interblock correlation. In the proposed method, we reduce bit-rate by defining an address transform function, which maps a VQ address of an input block which will be encoded into a new address in the reordered codebook by using side match error. In one case that an original address can be transformed into a new transformed address which is lower than the threshold value, we encode the new address of the transformed convector, and in the other case we encode the address of the original convector which is not transformed. Experimental results indicate that the proposed scheme reduces the bit-rate by 45~50% compared with the ordi-nary VQ method forimage compression, at the same quality of the reconstructed image as that of the ordinary VQ system.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.71-78
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• 2019

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.243-245
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• 2004

This paper proposes design and implementation for Seamless Handoff method between adapters in a system environment where both wired and wireless adapters are present First of all, by settingLayer 2 address of wired adapter to Layer 2address of wireless adapter, then generate virtual adapter on the above layer to make these two adapters operate on an IP address. Under the condition, when wired communication via the wired adapter gets disconnected while in service, wireless handoff occurs by mapping information on the wireless adapter to the virtual adapter. According to the method proposed in this paper, continuous session can be obtained even when handoff between wired and wireless adapters occurs at lower level in an application where both IP address and Port address are used to maintain session since If address does not change.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.10a
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• pp.234-237
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• 2016

Address Resolution Protocol (ARP) is used for mapping a network address to physical address in many network technologies. However, since ARP protocol has no security feature, it always abused by attackers for performing ARP-based attacks. Researchers presented many technologies to improve ARP protocol, but most of them require a high implementation cost or scarify the network performance for using ARP protocol securely. In this paper, we present an ARP-disabled network system to neutralize the ARP-based attacks. "ARP-disabled" means suppress the ARP messages like request, response and broadcast messages, but not the ARP table. In our system, ARP tables are used for managing static ARP entries without prior knowledge (e.g. IP, MAC list of client devices). This is possible because the MAC address was designed to be derived from IP address. In general, our system is safe from the ARP-based attacks even the attacker has a strong power. Moreover, we saved network bandwidth by disabling the ARP messages.

• Journal of the Korea Society of Computer and Information
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• v.22 no.12
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.15-18
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• 2003

Flash memory becomes more important for its fast access speed, low-power, shock resistance and nonvolatile storage. But its native restrictions that have limited 1ifetime, inability of update in place, different size unit of read/write and erase operations need to managed by FTL(Flash Translation Layer). FTL has to control the wear-leveling, address mapping, bad block management of flash memory. In this paper, we focuses on the fast access to address mapping table and proposed the way of faster valid page search in the flash memory using the VPLT(Valid Page Lookup Table). This method is expected to decrease the frequency of access of flash memory that have an significant effect on performance of read and block-transfer operations. For the validations, we implemented the FTL based on Windows CE platform and obtained an improved result.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.2
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• pp.90-102
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• 2010

Flash memory has been widely used as an important storage device for consumer electronics. For the flash memory-based storage systems, FTL (Flash Translation Layer) is used to handle the mapping between a logical page address and a physical page address. Especially, log buffer-based FTLs provide a good performance with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping structure between data blocks and log blocks, called associativity. While previous works use static associativity fixed at the design time, we propose a new log block mapping scheme which adjusts associativity based on the run-time workload. Our proposed scheme improves the I/O performance about 5~16% compared to the static scheme by adjusting the associativity to provide the best performance.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.9-17
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• 2019

In this paper, we propose a block mapping technique applicable to NAND flash memory. In order to use the NAND flash memory with the operating system and the file system developed on the basis of the hard disk which is mainly used in the general PC field, it is necessary to use the system software known as the FTL (Flash Translation Layer). FTL overcomes the disadvantage of not being able to overwrite data by using the address mapping table and solves the additional features caused by the physical structure of NAND flash memory. In this paper, we propose a new mapping method based on the block mapping method for efficient use of the NAND flash memory. In the case of the proposed technique, the data modification operation is processed by using a blank page in the existing block without using an additional block for the data modification operation, thereby minimizing the block unit deletion operation in the merging operation. Also, the frequency of occurrence of the sequential write request and random write request Accordingly, by optimally adjusting the ratio of pages for recording data in a block and pages for recording data requested for modification, it is possible to optimize sequential writing and random writing by maximizing the utilization of pages in a block.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2005.11a
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• pp.295-303
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• 2005

Semantic Web and its related technologies have been opening the era of information sharing via Web. In the meantime, there are several huddles to overcome toward the new era and one of the major huddles is information integration issue unless we build and use a single unified but huge ontology which address everything in the world. Particularly in e-business area, information integration problem must be a great concern in search and comparison of products from various internet shopping sites and e-marketplaces. To overcome such an information integration problem, we propose an ontology driven mapping algorithm between heterogeneous product classification and description frameworks. We also perform comparative evaluation of the proposed mapping algorithm against a well-known ontology mapping tool, PROMPT.