• Smart Structures and Systems
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• v.25 no.4
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• pp.401-408
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• 2020

This paper deals with the problem of global stabilization for a class of nonlinear control systems. An effective approach is proposed for controlling the system interaction of structures through a combination of parallel distributed compensation (PDC) intelligent controllers and fuzzy observers. An efficient approximate inference algorithm using expectation propagation and a Bayesian additive model is developed which allows us to predict the total number of control systems, thereby contributing to a more adaptive trajectory for the closed-loop system and that of its corresponding model. The closed-loop fuzzy system can be made as close as desired, so that the behavior of the closed-loop system can be rigorously predicted by establishing that of the closed-loop fuzzy system.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.6
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• pp.494-501
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• 2001

In this paper an ANFIS(Adativo Neuro-Fuzzy Inference System)- based fault detection and diagnosis for a closed loop control system is proposed. The proposed diagnostic system contains two ANFIS. One is run as a parallel model within the model in closed loop control(MCL) and the other is run as a series-parallel model within the process in closed loop(PCL) for the generation of relevant symptoms for fault diagnosis. These symptoms are further processed by another classification logic with simple rules and neural network for process and controller fault diagnosis. Experimental results for a DC shunt motor control system illustrate the effectiveness of the proposed diagnostic scheme.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.5
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• pp.1-8
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• 2013

This paper implements an integrated vehicle chassis system of ACC(Adaptive Cruise Control) and LKS(Lane Keeping System) based on OSEK OS to vehicle operating system and analyzes its performance through experiments. In recent years active safety and advanced driver assistance system has discussed to improve safety of vehicle. Among the rest, We integrate ACC that controls longitudinal velocity of vehicle and LKS that assists a vehicle in maintaing its driving lane, then implement integrated control system in vehicle. Implemented control system uses OSEK/VDX proposed standard, which is aiming at reusability and safety of software for vehicle and removal hardware dependence of application software. Redesigned control system based on OSEK OS, which is supported by OSEK/VDX, can manage real-time task, process interrupt and manage shared resource. We show by results performed EILS(ECU-In-the-Loop Simulation) that OSEK OS-based integrated controller of ACC and LKS is equivalent conventional integrated controller of ACC and LKS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.379-385
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• 2015

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1666-1672
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• 2019

A closed loop wireless transmission method adaptive to mobile unit speed is proposed in this paper. A mobile communication node measures the mobile speed based on the transmitted pilot signals through Doppler frequency estimation, and it changes the transmission period of pilot signals as per estimated mobile speed adaptively. The pilot signals with the different transmission periods are transmitted using the different PN sequences with the previous ones without any explicit information about the new period. The corresponding receiver node can detect and extract the transmitted pilot signals through blind search of the transmitted PN sequences of the pilot signals, and it can demodulate and decode the transmitted information using the channel estimation results based on the detected pilot signals. The performance of the proposed method had been analyzed through the simulation under the fading channel environments and compared with the previous methods. The simulation results showed performance improvement of the proposed method over the existing ones.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.963-966
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• 1998

In this paper, a fingerprint classification algorithm is presented. Fingerprint types are classified into five categories: arch, tented arch, left loop, right loop and whorl. Singular points (cores and deltas) are detected using Poincare index on the directional image smoothed by adaptive window size. The method is shown to be robust to the variation of fingerprint image qualaity.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.354-356
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• 2013

ITU와 ISO/IEC가 공동으로 UHD급 영상 부호화를 위해 표준화를 진행하고 있는 HEVC 코덱은 H.264/AVC 대비 2배 이상의 압축 효율을 갖는 것을 목표로 정하고 있다. HEVC(High Efficiency Video Coding)는 In-Loop Filter 기술로 H.264/AVC에서 사용하고 있는 Deblocking Filter와 새롭게 추가 된 SAO(Sample Adaptive Offset)를 사용하고 있다. 본 논문에서는 HEVC의 In-Loop Filter 기술 중 하나인 SAO의 기술의 EO에서 Category를 조금 더 정확하게 판단하여 분류하는 방법을 제안을 한다.

• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.261-270
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• 2013

A stereoscopic 3D video service is able to provide a 3D video service while keeping backward compatibility with the existing 2D video service. In the terrestrial digital television (DTV) system, a stereoscopic video codec is required to have high coding efficiency in order to provide a 3D video service in the same channel capacity. A hybrid codec consisting of MPEG-2 for base video and H.264/AVC or HEVC for 3D auxiliary video is considered. Furthermore, Non-Real-Time (NRT) delivery of stereoscopic video is also considered as a service scenario for 3DTV services to overcome the limited bandwidth. In this paper, we propose a stereoscopic video coding scheme using adaptive loop filter (ALF) which had been considered in HEVC as a pre-/post-filter for enhancing coding efficiency in NRT-based 3DTV services. In order to apply ALF as a post-filter to the reconstructed additional view coded by H.264/AVC, we devise a method in which ALF is adaptively applied based on a structure determined by using macroblock (MB) coding information such as MB mode type and reference index instead of coding unit (CU) structure on which ALF is applied in the HEVC. Experimental results shows that the proposed stereoscopic video coding scheme applying ALF obtains up to 24.9% gain of bit saving.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.295-298
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• 2014

In this paper, an efficient design of HEVC Adaptive Loop Filter(ALF) for filter coefficients estimation is proposed. The ALF performs Cholesky decomposition of $10{\times}10$ matrix iteratively to estimate filter coefficients. The Cholesky decomposition of the ALF consists of root and division operation which is difficult to implement in a hardware design because it needs to many computation rate and processing time due to floating-point unit operation of large values of the Maximum 30bit in a LCU($64{\times}64$). The proposed hardware architecture is implemented by designing a root operation based on Cholesky decomposition by using multiplexer, subtracter and comparator. In addition, The proposed hardware architecture of efficient and low computation rate is implemented by designing a pipeline architecture using characteristic operation steps of Cholesky decomposition. An implemented hardware is designed using Xilinx ISE 14.3 Vertex-6 XC6VCX240T FPGA device and can support a frame rate of 40 4K Ultra HD($4096{\times}2160$) frames per second at maximum operation frequency 150MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.