• Journal of Electrical Engineering and Technology
• /
• v.10 no.5
• /
• pp.1989-2000
• /
• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.16 no.4
• /
• pp.479-484
• /
• 2006

This paper discusses a fitness of the control on intersection using fuzzy analytic hierachy process. The validity of control of traffic signal on intersection is the fitness of phase and cycle on the intersection. The validity of the controller is cleared by the comparison of the delay time of vehicle. Fuzzy analytic hierachy process clears the grade of validity of the fixed cycle time controller and adaptive fixed cycle time and fuzzy trafic controller and proposes a new control type a traffic signal by this fuzzy analytic hierachy process.

• Biomedical Science Letters
• /
• v.10 no.4
• /
• pp.435-445
• /
• 2004

The characteristics of the testis and the annual cycle of the seminiferous epithelium of the Miniopterus schreibersi fuliginosus were examined by optical microscopy. The testis weight and diameter of the seminiferous tubules were increased gradually from May to July, and the highest activity was observed in August. The size then decreased rapidly from October. Spermatogenesis began in May, peaked in August, and was suspended from October to April in the following year. Spermatocytogenesis were produced from May to July. Spermiogenesis occurred from August to September. In particular, immature spematogenic cells in the seminiferous tubules were engulfed by the phagocytosis of Sertoli cells in October. From November to April, the seminiferous tubuly contained only Sertoli cells and Ad spermatogonia. Therefore, the periodic changes in the seminiferous epithelium of M. S. fuliginosus suggest that a long hibernation is an adaptive strategy for the preservation of energy and the regulation of the breeding cycle.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.100-103
• /
• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.108-111
• /
• 2008

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder engine for real time Full HD video compression. Since there are 384 data coefficients which are sum of 376 AC coefficient and 8 DC coefficient per one macroblock, 384 coefficient have to be processed per one macroblock in worst case for real time processing. We propose an novel architecture which includes parallel architecture and pipeline processing, and reduction "0" in AC/DC coefficient table. To verify the proposed architecture, we develop the reference C for CAVLC and verified the designed circuit with the test vector from reference C code.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.237-240
• /
• 2005

This paper propose an novel CAVLC architcture for H.264 and designed the CAVLC module which can be used in AMBA based design. This designed module can be operated in 420 cycle for one-macroblock and support both long-start code method using Annex B.1 and RTP. To verify the CAVLC architecture, we developed the reference C from JM8.5 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 54MHz clock system, and has 14096 gate counts using Hynix 0.35 um TLM process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.12
• /
• pp.2647-2654
• /
• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Economic Geographical Society of Korea
• /
• v.16 no.4
• /
• pp.567-584
• /
• 2013

This study aims to explore an evolutionary path of the IT service industry in Fairfax County using the Cluster Adaptive Cycle model in economic geography. The analysis is based on detailed historical and industrial information obtained through a variety of data sources including local archival materials, economic census, and interviews. This study also performs a shift-share analysis during the period of 1990 to 2011. Using the adaptive cycle model, the local IT service industry is indicated by a trajectory of constant cluster mutation. The evolution of the local IT service industry has been closely related to federal government policy due to the regional specificity of the National Capital Region and the proximity of the Department of Defense. Although the economic downturn of the late 2000s, the local IT service industry has been notable resilience and adapted to a changing market and technological environment. This constant mutation of the local industry is resulted from not only high resilience which is based on the large government procurement market, the reinforcement of adaptive capacity of the local firms and the network of economic agents such as firm and supporting institutions, but also high flexibility of the knowledge-based service industry to a changing business environment.

• Proceedings of the Korean Society for Agricultural Machinery Conference
• /
• 1993.10a
• /
• pp.1222-1229
• /
• 1993

An advanced design environment , which is based on adaptive and knowledge -based finite elements (INTELMESH), has been developed. Unlike other approaches, INTEMMESH incorporates the information about the object geometry as well as the boundary and loading conditions to generate an ${\alpha}$-priori finite element mesh which is more refined around the critical regions of the problem domain. INTEMMESH is designed for planar domains and axisymmetric 3-D structures of elasticity and heat transfer subjected to mechanical and thermal loading . It intelligently identifies the critical regions/points in the problem domain and utilize the new concepts of substructuring and wave propagation to choose the proper mesh size for them. INTEMMESH generates well-shaped triangular elements by applying trangulartion and Laplacian smoothing procedures. The adaptive analysis involves the intial finite elements analyze and an efficient ${\alpha}$-posteriori error analysis involves the initial finite element anal sis and an efficient ${\alpha}$-posteriori error analysis and estimation . Once a problem is defined , the system automatically builds a finite element model and analyzes the problem though automatic iterative process until the error reaches a desired level. It has been shown that the proposed approach which initiates the process with an ${\alpha}$-priori, and near optimum mesh of the object , converges to the desired accuracy in less time and at less cost. Such an advanced design/analysis environment will provide the capability for rapid product development and reducing the design cycle time and cost.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.3B
• /
• pp.114-129
• /
• 2005

In this paper, we examine Interleaved Polling with Adaptive Cycle Time (IPACT) algorithm which was proposed to control upstream traffic for Gigabit Ethernet-PONs, and we analyze the performance of the gated service and the limited service of the IPACT mathematically. For the mathematical performance analysis, we model IPACT algorithm as a polling system and use mean-value analysis. We divide arrival rate λ value into three regions and analyze each region accordingly. We obtain average packet delay, average queue size and average cycle time of both the gated and the limited service. We compare analytical results with simulation to verify the accuracy of the mathematical analysis. Upon now, simulation analysis have been used to evaluate the performance of EPONs, which require much time sud effort. Mathematical analysis can be widely used in the design of EPON systems since system designers can obtain various performance results rapidly.