• BMB Reports
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• 제32권3호
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• pp.215-225
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• 1999

Phytochromes (with gene family members phyA, B, C, D, and E) are a wavelength-dependent light sensor or switch for gene regulation that underscore a number of photo responsive developmental and morphogenic processes in plants. Recently, phytochrome-like pigment proteins have also been discovered in prokaryotes, possibly functioning as an auto-phosphorylating/phosphate-relaying two-component signaling system (Yeh et al., 1997). Phytochromes are photochromically convertible between the light sensing Pr and regulatory active Pfr forms. Red light converts Pr to Pfr, the latter having a "switch-on" conformation. The Pfr form triggers signal transduction pathways to the downstream responses including the expression of photosynthetic and other growth-regulating genes. The components involved in and the molecular mechanisms of the light signal transduction pathways are largely unknown, although G-proteins, protein kinases, and secondary messengers such as $Ca^{2+}$ ions and cGMP are implicated. The 124-127 kDa phytochromes form homodimeric structures. The N-terminal half contains the tetrapyrrolic phytochromobilin for red/far-red light absorption. The C-terminal half includes both a dimerization motif and regulatory box where the red light signal perceived by the chromophore-domain is recognized and transduced to initiate the signal transduction cascade. A working model for the inter-domain signal communication within the phytochrome molecule is proposed in this Review.

• 전력전자학회논문지
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• 제20권1호
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• pp.65-71
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• 2015

This paper presents the efficiency analysis of a critical current mode interleaved PFC rectifier, in which each of three different semiconductor switches is employed as the active switch. The Si FET, SiC FET, and GaN FET are consecutively used with the prototype PFC rectifier, and the efficiency of the PFC rectifier with each different semiconductor switch is analyzed. An equivalent circuit model of the PFC rectifier, which incorporates all the internal losses of the PFC rectifier, is developed. The rms values of the current waveforms main circuit components are calculated. By adapting the rms current waveforms to the equivalent model, all the losses are broken down and individually analyzed to assess the conduction loss, switching loss, and magnetic loss in the PFC rectifier. This study revealed that the GaN FET offers the highest overall efficiency with the least loss among the three switching devices. The GaN FET yields 96% efficiency at 90 V input and 97.6% efficiency at 240 V, under full load condition. This paper also confirmed that the efficiency of the three switching devices largely depends on the turn-on resistance and parasitic capacitance of the respective switching devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.211-216
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• 전기학회논문지
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• 제59권2호
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• Smart Structures and Systems
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• 제9권2호
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• pp.189-206
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• 2012

This paper focuses on the actuation system combined with a piezoelectric transducer and an electric circuit, which leads to a new insight; the electric actuation system is equivalent to mechanical variable-stiffness actuation systems. By controlling the switch in the circuit, the electric status of the piezoelectric transducer is changed, and consequently a variable-stiffness mechanism is achieved on the electric actuator. This proposed actuator features a shift in the equilibrium point of force, while conventional electrically-induced variable-stiffness actuators feature the variation of the stiffness value. We intensively focus on the equilibrium shift in the actuation system, which has been neglected. The stiffness of the variable-stiffness actuator is periodically modulated by controlling the switch, to suppress the vibration of the system in an open-loop way. It is proved that this electric actuator is equivalent to its mechanical counterpart, and that the electrical version has some practical advantages over the mechanical one. Furthermore, another kind of electrically-induced variable-stiffness actuator, using an energy-recycling mechanism is also discussed from the viewpoint of open-loop vibration control. Extensive numerical simulations provide comprehensive assessment on both electrically-induced variable-stiffness actuators employed for open-loop vibration control.

• 전력전자학회논문지
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• 제22권2호
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• pp.140-149
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• 2017

This study proposes a new type of active-clamp forward-flyback converter with two transformers that operate in forward and flyback modes during on and off times, respectively, instead of not using an output inductor. The main switch can be turned on with zero-voltage switching (ZVS) using the leakage inductance of the transformer and the output capacitor of the main switch. The leakage inductance should be increased to ZVS. However, the ringing between the leakage inductance of the transformer and the parasitic output capacitance of the secondary side rectifier switches results in a serious voltage spike. A forward-flyback converter employing auxiliary inductor and auxiliary diode is proposed to overcome the problem. The operational principles are analyzed in detail and validated through experiments with a 385 V-to-53 V/37 A prototype.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.163-164
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• 2014

본 논문에서는 능동 클램프 회로를 이용한 위상천이 풀-브리지 컨버터(Phase-shift Full-Bridge Converter)의 스위치 제어 방법을 제안한다. 기존의 위상천이 풀-브리지 컨버터는 2차측 정류 스위치에서 스파이크 전압이 발생하며, 순환 전류(Circulating current)로 인한 도통 손실이 발생하는 단점을 지닌다. 위의 문제를 극복하는 회로로서 2차 측에 능동 클램프 회로를 적용하는 방법이 연구되었다. 하지만, 낮은 부하에서 클램프 커패시터의 전압이 상승하여, 2차 측 소자의 전압 스트레스가 증가하고, EMI 문제가 발생되는 단점을 지닌다. 본 논문에서는 위상천이 풀-브리지 컨버터의 2차 측에 능동 클램프 회로 및 동기 정류 스위치(Synchronous rectifier switch)를 적용하여, 클램프 커패시터의 전압 상승을 억제하는 해결 방안을 제시하며, 능동 클램프 회로의 스위치 제어 방법을 제안한다. 또한, 회로의 구조, 동작 원리 및 스위치 제어 방법을 설명하고, 모의 실험을 수행하여 타당성을 검증한다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.165-171
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• 2011

A Consider the dead man's switch installed in each and every locomotive cab, which support operational safety on railways around the world. The concept is very simple - every 150 to 180 seconds an illuminated push-button demands to be acknowledged so as to know that the Train Driver is alive and active. In the absence of a response over a period of minutes, the vigilance control will automatically apply the train brakes and bring the train to a stand. If we multiply the resetting of the vigilance control 60 times per hour by a 10-hour shift it equals 600 presses of the button during the shift that a Train Driver must pay attention to and acknowledge. This adds a fair bit of pressure on the train driver's job, particularly when he/she is driving through stations, with passengers moving about on platforms in an environment of complex signaling arrangements - all the while looking out for restricting signals. From this perspective, the Vigilance System's demand to be acknowledged every 150/180 seconds is disturbing and can unnecessarily take a driver's attention away from what is happening outside the confines of the cab. A much more dramatic situation can happen when a train driver is driving hour after hour at night when, by Mother's Nature request - people need to sleep. Experience and research shows that the the dead man's switch can be pressed by train driver in a state of deep relaxation and 'micro-sleep'. The vigilance control system which is applied to reduce the drive load considering bio-response multiple unit train is proposed.

• Journal of Power Electronics
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• 제4권4호
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• pp.237-245
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• 2004

In this paper, a two-switch high frequency flyback transformer linked zero voltage soft switching PWM DC-DC power converter implemented for distributed DC- feeding power conditioning supplies is proposed and discussed. This switch mode power converter circuit is mainly based on two main active power semiconductor switches and a main flyback high frequency transformer linked DC-DC converter in which, two passive lossless quasi-resonant snubbers with pulse current regeneration loops for energy recovery to the DC supply voltages composed of a three winding auxiliary high frequency pulse transformer, auxiliary capacitors and auxiliary diodes for inductive energy recovery discharge blocking due to snubber capacitors are introduced to achieve zero voltage soft switching from light to full load conditions. It is clarified that the passive resonant snubber-assisted soft switching PWM DC-DC power converter has some advantages such as simple circuit configuration, low cost, simple control scheme, high efficiency and lowered noises due to the soft switching commutation. Its operating principle is also described using each mode equivalent circuit. To determine the optimum resonant snubber circuit parameters, some practical design considerations are discussed and evaluated in this paper. Moreover, through experimentation the practical effectiveness of the proposed soft switching PWM DC-DC power converter using IGBTs is evaluated and compared with a hard switching PWM DC-DC power converter.

• 한국통신학회논문지
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• 제37권2B호
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• pp.130-137
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• 2012

본 논문은 백본 망에서 발생하는 에너지를 절감하기 위하여 LPI(Low Power Idle)를 이용하는 OBS 코어 및 에지 라우터 구조를 제안하고 이를 평가한다. 제안한 LPI를 이용하는 코어 라우터는 코어 라우터 라인 카드와 BCP 스위치, 버스트 스위치, 스위치 제어기 및 LPI 기능을 위한 Sleep/Wake 제어기로 구성된다. 망 부하가 낮을 때 네트워크 제어 패킷을 수신한 Sleep/Wake 제어기는 코어 라우터 라인 카드의 수면/활성 상태를 제어함으로써 에너지를 절감 할 수 있다. 에지 라우터는 액세스 라인 카드 스위치, SCU 그리고 OBS 에지 라우터 라인 카드로 구성된다. 에지 라우터에서 LPI 기능은 네트워크 수준 제어를 통하여 에지 라우터 라인 카드 개별적으로 수행되며 버스트를 생성하는 동안 에지 라우터 라인 카드의 PHY/Transceiver를 수면 상태로 천이시킴으로서 에너지 절감을 할 수 있다. 제안된 코어 및 에지 라우터 구조의 에너지 절감 성능 평가를 위하여 본 논문에서는 제안된 라우터 구조의 전력 소모율을 비교/분석하였으며, OPNET을 이용한 시뮬레이션을 수행하여 코어 라우터와 에지 라우터 라인 카드의 PHY/Transceiver의 수면시간 관점에서 코어 및 에지 라우터의 에너지 절감 성능을 평가하였다.