• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.6
• /
• pp.1185-1194
• /
• 1997

It is necessary to control the frame memory to capture, edit and display images. This paper presents the free-scale image capture processor size of which is user-defined, compared to the conventional image capture processor size of which is fixed 1/2, 1/4 and full size. User-defined scale data is fed into this system, which generates the gating pulses and gates the inputted image data. This system also controls the 4M DRAM instead of frame meamory. And stored gated image data are displayed on the TV monitor. We designed the scalable image capture parts and DRAM controller with ACTEL FPGAs, simulated the circuits with Viewlogic and fusing ACTEL A1020B chips. We confirmed the whole operation with beadboard which composed of "Philips TV Chipset" and designed FPGA chips.PGA chips.

• Journal of Satellite, Information and Communications
• /
• v.11 no.3
• /
• pp.65-71
• /
• 2016

Currently developing the OBC of the next-generation LEO satellite by Korea Aerospace Research Institute adopts the LEON2-FT/AT697F processor to achieve high performance. And various communication devices such as SpaceWire, MIL-STD-1553B, DMAUART and CAN Master are integrated to the separated standard communication FPGAs within the OBC, where they can be controlled by the processor and flight software (FSW) through PCI interface. The Actel 1553BRM IP core is used for the 1553B in the next-generation LEO OBC and the B1553BRM wrapper from Aeroflex Gaisler is used for connecting it to the AMBA bus in FPGA. This paper presents the design and development of PCI-based 1553B communication software, and describes the handling mechanism of 1553B operation in FSW task level. Also it shows the test results on real-hardware and simulator.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.35 no.6
• /
• pp.556-563
• /
• 2007

The current trend of low cost ultra-small satellites is to utilize Commercial Off the Shelf (COTS) parts to save cost, and accordingly, Command and Data Handling (C&DH) that operates the satellite and collects/processes the data is also designed and developed around commercial controllers. However, functionalities of commercial controllers are limited according to the specs outlined by the manufacturer. In order for the commercial controllers to be used for satellites where variety of interfaces is required, a separate interface circuit is required. Therefore, a Multi Digital Data Control System (MDDCS) using Field Programmable Gate Array (FPGA) has been developed in order to expand multiple digital interfaces that are not supported by the commercial controller, and also to compensate for SEU. This has been implemented on Actel A3P1000 using Very High Speed Integrated Circuits Hardware Description Language (VHDL).

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.52 no.1
• /
• pp.20-27
• /
• 2003

In this study, we designed and made Ultrasonic motor-digital multi controller(USM-DMC) using FPGA chip, A54SX72A made in Actel Corporation. By the minute, USM-DMC can adjust the frequency, duty ratio, and phase difference parameters of USM by digital input to be each 11bit from PC. Therefore, when we use this controller, it is possible to apply typical three parameters individually as well as multi-parameters simultaneously to control the speed and the torque. What is more, the strongest point is that it can trace frequency based on optimized frequency as compared with the phase difference because we can input optimized resonant frequency while in motoring. And we test the speed of USM with the adjustment of multi-parameters, the phase difference-frequency. As the result of the test, in the case of the multi-parameters of the phase difference and frequency, the speed characteristic is more linear and stable, and wider in the range of control than the single-parameter of the phase difference or the frequency.

• Journal of IKEEE
• /
• v.2 no.2 s.3
• /
• pp.225-232
• /
• 1998

Currently NTSC, PAL, and SECOM are widely used for TV broadcasting systems. In Korea, NTSC has been used to reduce transmission bandwidth and broadband flickers using the Interlaced scanning method. Image data in the Interlaced scanning method require De-interlacing compensation for PC-based multimedia applications. The existing compensation algorithms such as ZOI, FOI, and ELA provieds simple computations and effective image compensation while the PSNR is low and horizontal and vertical edges are hardly detected. In this paper, the ADI(Adaptive De-Interlacing) algorithm that can increase PSNR and detect horizontal and vertical edges is proposed and a hardware system is implemented using three ACTEL 1020B FPGA chips. The system consists of the algorithm part implemented using two FPGAs and the memory control part implemented using rest one. Also the system operation is investigated for real time processing.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.6
• /
• pp.1533-1545
• /
• 1996

In this paper, the design and implementation of echo canceller with new variable step size algorithm is discussed. The method used in the new algorithm is to periodically adopt the test function which helps an optimal coefficient tracking. This algorithm outperforms LMS and VS algorithms in convergence speed and steady state error. As the period of test function is decreased, the speed of convergence is improved, but the number of calculation is increased, then the trade off between these parameters must be considered. Simulation results show new algorithm outperforms LMS and VS algorithms in convergence rate. For the design of hardware, circuit is designed with VHDL, and synthesized with Act1 withc is a FPGA library of ActelTM in use of synovation of InterGraph$^{TM}$. Verification of the synthesized circuit is carried out with simulator DLAB. The circuit based on the algorithm which is suggested in this paper calculated 7 radix places of inary number. A simulation data for the verification is based on the data of algorithm simulation. When the same input data is applied to the both simulation, output results of circuit simulation had slight difference in compare with that of algorithm simulation. The number of used gate is about 5,500 and We have 5.53MHz in maximum frequency.y.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.1 no.1
• /
• pp.21-33
• /
• 1997

This dissertation deals with the design and VLSI implementation of the MTP(Multimedia Transport Protocol) protocol for the high speed networks. High throughput, functional diversity and flexible adaptation are key requirements for the future transport protocol. However it is very difficult to satisfy all these requirements simultaneously. Fortunately, the future networks will be very reliable. It means that the future transport protocol will usually perform some fixed functions without the protocol state information. According to this concept, we proposed and designed the MTP protocol that is consisted of Information Plane and Control Plane. Information Plane performs some fixed functions that are independent of the protocol state information as far as no error. However Control Plane manages the protocol state information and controls the operation of Information Plane. Our MTP protocol was finally implemented as an FPGA chip using the VHDL. We built a testbed for verification of the implemented protocol, and it was shown that the MTP protocol worked correctly and made a throughput of about 800 Mbps. Our future works include the addition of multiplexing and multicasting capabilities to our protocol for multimedia applications.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.33 no.7
• /
• pp.98-105
• /
• 2005

In this paper, the decryption function of CCSDS telecommand of CTU EQM for the security of communications satellite was verified. In order to intensify the security level of DES CFB decryption algorithm applied to CTU EM, 3DES CFB decryption algorithm using three keys is implemented in the CTU EQM. As the decryption keys increased due to the 3DES algorithm, the keys and IV are stored in PROM memory, and used for the telecommand decryption by taking the keys and IVs corresponding to the selected key and IV indexes from the memory. The operation of the 3DES CFB is validated through the timing simulation of 3DES CFB algorithm, and then the 3DES CFB core implemented on the A54SX32 FPGA. The test environment for the telecommand decryption verification of the CTU EQM was built up. Through sending and decrypting the encrypted command, monitoring the opcodes, and confirming LED on/off by executing the opcodes, the 3DES CFB telecommand decryption function of the CTU EQM is verified.

• Journal of the Korean Home Economics Association
• /
• v.12 no.34
• /
• pp.743-769
• /
• 1974

Au debut I'habit Iiturgique ne differait de I'habit de fete du simple citoyen que par sa richesse. C'est seulement quand, dans la vie courante, on adopta la robe courte que le vetememt liturgique commenca a se distinguer, meme par la forme, du costume civil. Les ornements liturgiques, en effet, ne sont qu'une forme stylisee de l'habit de fete de la fin de l'Empire Romain (du IIIeme au Veme siecle). Pour une ceremonie religieuse on se presente bien habille. Le meme sentiment de respect des choses sacrees a amene deja, vers la fin de l'antiquite chretienne, a donner au pretre un vetememt liturgique special. Pour celebrer la messe, le pretre revet par-dessus sa soutane un costume special, compose de l'amict, de l'aube, du cordon, du manipule, de l'etole et de la chasuble. Aux messes solennelles, les eveques ajoutent a ces ornements des bas et sandales, des gants, la tunique et la dalmatique avee la mitre ; en certain cas, les archeveques y joingnent le pallium. Aux messes solennelles, le diacre porte sur ; l'aube le manipule et la tunique. De ces pieces du costume liturgique, on dira brievement, apres leur emploi et leur forme actel, l'origine et l'histoire, mais seulement apres avoir marque les lignes generales parition et des transformations du costume liturgique dans son ensemble. L'evolution du costume liturgique a partir du XIIIeme siecle peut se resumer en quelques mots en raison souvent de la lourdeur des riches etoffes (velours et brocarts) et de l'importance donne a la decoration, toujours par rechereche d'une plus grande commodite on a abandonne lentement d'abord, puis rapidement adapte a partir du XVI eme siecle, les formes amples pour des formes courtes et etriquees. Il faut faire quelques exceptions qui marquent l'influence des gouts decoratifs de gouts epoque : La periode de 1700 a 1850 marque la complete decadence du costum liturgique. On a depuis essaye de lui rendre sa beaute et aussi sa signification symbolique, par un retour aux etoffes et a la decoration de la deuxieme partie du moyen age. Souhations que, sous la direction des liturgistes, en respectant l'essentiel de la liturgie aujourd'hui, avec le concours d'artistes epris du sens liturgique et des connaisseurs des tradtions et de toutes les ressources actuelles on trouve des costumes liturgiques adaptes a notre temps dans un style plus simple et correspondant au besoins actuels.

• Proceedings of the KIEE Conference
• /
• 2002.06a
• /
• pp.187-190
• /
• 2002

In contrast to conventional electromagnetic motor, USM(Ultrasonic Motor), as piezoelectric ceramic applying ultrasonic mechanical vibration and as frictional-movement type motor, get rotational torque by elastic friction between stator and rotator, The USM, which is small motor without iron cores and coil as a simple structure, has little load weight, has character of high torque at low speed, and can apply a direct drive type without deceleration gear as low speed type. A response of USM from control input is satisfactory, and also generates much torque in low speed driving, and holding torque is much without supplying power. In this study, I designed and made Ultrasonic motor-digital multi controller(USM- DMC) using FPGA chip, A54SX72A made in Actel Corporation. By the minute, USM-DMC can control frequency, duty ratio, and phase difference of USM by llbit digital input from Pc. Therefore, when we use this controller, we can apply to typical parameter, frequency, phase difference, and voltage parameter, to control as well as we can do mixing control like phase-frequency, phase-voltage, frequency-voltage, frequency-phase-voltage, What is more, the strongest point is that it can trace frequency based on optimized frequency because we can input optimized resonant frequency while in motoring.